MT9072AB datasheet(62/275 Pages) ZARLINK

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MT9072

Data Sheet

Zarlink Semiconductor Inc.

7.2.4

E1 Timeslot 0 CRC-4 NFAS Receive from PCM30 to DSTo

Non-Frame Alignment Signal (NFAS) bits on the receive PCM30 link (bit positions one to eight of timeslot 0 of odd

CRC-4 frames 1, 3, 5, 7, 9, 11, 13, 15) are sourced to the ST-BUS DSTo stream.The data to DSTo is mapped

unaltered from the receive PCM30 link as shown in Table 20.

7.3

T1 Bit Oriented Message

Bit Oriented Messages can be sent on the FDL in ESF mode.

Bit - Oriented Messages may be transmitted via the TxBOM register (Y07) and received in the RxBOM (Y12).

Transmission is enabled by setting bit 2 - BOMEn in the HDLC &Data link Control Word(Y06). Bit - oriented

messages may be periodically interrupted (up to once per second) for a duration of up to 100 milliseconds. This is

to accommodate bursts of message - oriented protocols. Table 21 shows the messages that can be sent and

received according to T1.403. The transmit data link will contain the repeating serial data stream 111111110xxxxxx0

where the byte 0xxxxxx0 originates from the user programmed register “Transmit Bit Oriented Message” - Y07. The

receive BOM register “Receive Bit Oriented Message” - Y12, will contain the last received valid message (the

0xxxxxx0 portion of the incoming serial bit stream). To prevent spurious inputs from creating false messages, a new

message must be present in 8 of the last 10 appropriate byte positions before being loaded into the receive BOM

Line status and Timer Mask (Y45) may occur. Bit oriented messages are only applicable in the ESF mode.

A Bit oriented match register is available RXBOMM(Y08) and a maskable interrupt can be generated when the

received Bit Oriented Message matches the contents of RXBOMM; the mask can be enabled by writing a ‘0’ to bit 3

of the Receive Line and Timer Interrupt Mask Register (Y45).

ST-BUS DSTi

PCM30 Transmit

CRC-4

Frame

Timeslot

Data Bits (B7-B0)

Timeslot

CRC-4

Frame

Data Bits (B1-B8)

All NFAS

P1, P2, P3, Sa4, Sa5, Sa6,

Sa7, Sa8

All NFAS

P1, P2, P3, Sa4, Sa5, Sa6,

Sa7, Sa8

Note 1. For 2.048 Mbit/s operation, n=0.

Note 2. For 8.192 Mbit/s operation, n =0,1,2,3 where n corresponds to the framer number (i.e., n=0=framer 0... n=3= framer 3).

Note 3. To source the NFAS, Sa bits from DSTi, ST-BUS mode access must be enabled (SA4SS to SA8SS = 10 register address

Y08.

Table 19 - Transmit PCM30 National Bits from ST-BUS 2.048 Mbit/s or 8.192 Mbit/s DSTi (E1)

ST-BUS DSTo

PCM30 Receive

CRC-4

Frame

Timeslot

Data Bits (B7-B0)

Timeslot

CRC-4

Frame

Data Bits (B1-B8)

All NFAS

P1, P2, P3, Sa4, Sa5, Sa6,

Sa7, Sa8

All NFAS

P1, P2, P3, Sa4, Sa5, Sa6,

Sa7, Sa8

Note 1. For 2.048 Mbit/s operation, n=0.

Note 2. For 8.192 Mbit/s operation, n =0,1,2,3 where n corresponds to the framer number (i.e., n=0=framer 0... n=3= framer 3).

Note 3. For these functions to be valid, NFAS DSTi ST-BUS mode access must be enabled (SA4SS to SA8SS register address Y08).

Note 4. For these functions to be valid, the Timeslot Control Registers must be disabled (all bits=0 register address Y90-YAF).

Table 20 - Receive PCM30 National Bits to ST-BUS 2.048 Mbit/s or 8.192 Mbit/s DSTo (E1)

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