MT9072AB datasheet(36/275 Pages) ZARLINK

36 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

197

Intel / Motorola. High configures the processor interface for Intel type

of parallel non-multiplexed processors where RD and WR pins are

used. Low configures the processor interface for Motorola type of

parallel non-multiplexed processors where R/W and DS pins are used.

See Figure 28 and Figure 29.

198

RESET

Reset. When zero, all eight framers of the MT9072 are in a reset

condition where all registers are set to their default values. When one,

all eight framers of the MT9072 operate normally where all registers

may be programmed by the external processor. A valid reset condition

requires this input to be held low for a minimum of 100 ns. This input

should be set to zero during initial power up, then set to one.

199

TAIS

Transmit Alarm Indication Signal. When zero, all eight framers of

the MT9072 transmit an all ones signal (AIS) at the TPOS and TNEG

output pins. When one, all eight framers of the MT9072 transmit data

normally. This input is typically set to zero during initial power up, then

set to one.

200

TxMF

Transmit Multiframe Boundary. This pin accepts a frame pulse that

sets the multiframe boundary for the framer transmitters. The device

will generate its own multiframe boundary if this pin is held high. The

TxMF pin is held high in most applications. This input is common for all

eight framers, and is enabled on a per framer basis with a control

modes.

In T1 mode the frame pulse applied to this pin sets the transmitted

D4/ESF multiframe boundary. The falling edge of this frame pulse

identifies basic frame 0 on the ST-BUS data stream (DSTi). This input

is enable with control bit TxMFSEL (Address YF1). See Figure 41.

In E1 mode the frame pulse applied to this pin sets the transmitted

channel associated signaling (CAS) multiframe boundary or the

transmitted CRC-4 multiframe boundary. The falling edge of this frame

pulse identifies basic frame 0 on the ST-BUS data stream (DSTi) of the

16 frame multiframe. This input is enabled with control bit MFBE

(Address Y02). See Figure 60.

201

RSV

This pin should be tied low.

202

RSV

This pin should be tied low.

203

RSV

This pin should be tied low.

204

TDI

IPu Test Data Input. One of five signals (TDI, TDO, TMS, TCK & TRST)

making up the Test Access Port (TAP) of the IEEE 1149.1-1990

Standard Test Port and Boundary-Scan Architecture. The TAP

provides access to test support functions built into the MT9072. The

TAP is also referred to as a JTAG (Joint Test Action Group) port.

Pin Description (continued)

Pin #

Name

Type

Description (see Notes 1 to 7)

LQFP

LBGA

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