MT9072AB datasheet(45/275 Pages) ZARLINK

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MT9072

Data Sheet

Zarlink Semiconductor Inc.

5.0

Framing

5.1

T1 Framing

DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit - the S-bit. The S-bit

contains a fixed repeating pattern used to enable DS1 receivers to delineate frame boundaries. S-bits are inserted

once per frame at the beginning of the transmit frame boundary. The DS1 frames are further grouped in bundles of

frames, generally 12 (for D4 applications) or 24 frames deep (for ESF - extended superframe applications). The

registers for controlling and observing the framing algorithms are presented in the Table 7.

Address

Description

Y00

Framing Mode Select

This register is used for selecting the different framing modes

from ESF to D4 or T1DM. The register is also used for selecting

reframe criteria.

Y10

Synchronization and Alarm

Status Word.

This register provides the real time status of the receive framing

algorithm as to basic frame synchronization and multiframe

synchronization.

Y16

MFOOF Counter

This status register increments every 1.5 msec for D4 mode or

every 3 msec for ESF mode when the basic frame

synchronization is lost.

Y17

Framing Bit Error Counter

This counter counts the Ft errors in ESF mode and Ft+Fs error in

D4 and T1DM.

Y19

CRC-6 Error Counter

This counter counts the CRC-6 errors by comparing the

calculated CRC-6 with the CRC-6 bits in the ESF frame.

Y1A

Out of Frame Counter and

Change of Frame Counter

The out of frame counter is incremeted with every loss of receive

frame synchronization. The change of frame counter is

incremented with every shift in the frame alignment position.

Y24

Receive Sync and Alarm Latch

This register contains latched bits for events related to framing

such as framing bit errors.

Y28

Framing Bit Error Count Latch

This counter is a latched version of Y17, the value of this counter

is updated every 1 sec.

Y2A

CRC-6 Error Counter Latch

This counter is a latched version of Y19, the value of this counter

is updated ever 1 sec.

Y2B

Out of Frame Counter Latch and

Change of Frame Counter Latch

This counter is a latched version of Y19, the value of this counter

is updated ever 1 sec.

Y2C

MFOOF Counter Latch

This counter is a latched version of Y16, the value of this counter

is updated ever 1 sec.

Y34

Receive Sync Interrupt Status

This register captures interrupt events related to the receiver

framer such as Framing Bit error. Interrupts can be generated by

setting appropriate masks.

Y44

Receive Sync Interrupt Status

This mask corresponds to the Y34 status register. Writing a “0”

unmasks an interrupt.

Table 7 - Registers Related to Framing Mode for the MT9072 (T1)

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