MT9072AB datasheet(94/275 Pages) ZARLINK

94 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

14.2.4

E1 Pseudo-Random Bit Sequence (PRBS) Testing

The MT9072 includes both a pseudo random bit sequence (PRBS) generator of type (215-1), and a reverse PRBS

generator (decoder), which operates on a bit sequence, and determines if it matches the transmitted PRBS type

(215-1). Bits which don’t match are counted by an internal error counter. This provides for powerful system

debugging and testing without additional external hardware.

If control bit ADSEQ (register address Y01) is zero, any transmit (internal DSTi) timeslot or combination of transmit

timeslots may be connected to the PRBS generator. Timeslot n is selected by setting the TTSTn bit in the Timeslot

n Control Register (address Y90-YAF), where n is 0 to 31. Any data sent on DSTi is overwritten on the selected

timeslots.

Similarly, if control bit ADSEQ is zero, any DSTo receive timeslot or combination of receive timeslots may be

connected to the PRBS decoder. Timeslot n is selected by setting the RRSTn bit in the Timeslot n Control Register

(register address Y90-YAF), where n is 0 to 31. Data on DSTo is not affected.

PRBS data is distributed to the transmit channels sequentially one byte at a time. Consequently, the data received

must be in the same order that it was sent, in order for the PRBS decoder to correctly operate on the data.

The number of transmit timeslots must match the number of receive timeslots, and the order of the transmit

timeslots must match the order of the receive timeslots. This will ensure that the sequential data bytes received by

the PRBS decoder are in the correct order. Consequently, particular care must be taken when using an external

loopback where the channel order may be reversed, or where the data has passed through a digital switch which

doesn’t buffer all channels to the same degree.

The PRBS decoder must have sufficient data pass through it before it begins to operate correctly, therefore, the

errors generated by the decoder immediately following start-up should be ignored.

If the PRBS testing is performed in an external loop around using Timeslot Control, then both Timeslot Control bits

TTSTn and RRSTn should also be set.

14.2.5

E1 A-law Milliwatt

If the control bit ADSEQ is one (register address Y01), the A-law digital milliwatt sequence (Table 48), defined by

G.711, is available to be transmit on any combination of selected channels. The channels are selected by setting

the TTSTn control bit (register address Y90-YAF). The same sequence is available to replace received data on any

combination of DSTo channels. This is accomplished by setting the RRSTn control bit (register address Y90-YAF)

for the corresponding channel. Note that bit 1 is the sign bit and is sent first.

PCM30 Payload Data

Hex

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

00110

100

00100

001

00100

001

00110

100

10110

100

10100

001

10100

001

10110

100

Table 48 - A-Law Digital Milliwatt Pattern (E1)

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