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MT9072AB датащи(PDF) 43 Page - Zarlink Semiconductor Inc |
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MT9072AB датащи(HTML) 43 Page - Zarlink Semiconductor Inc |
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43 / 275 page ![]() MT9072 Data Sheet 43 Zarlink Semiconductor Inc. 4.0 PCM30 Interface (E1) 4.1 E1 Interface to the System Backplane PCM30 (E1) basic frames are 256 bits long and are transmitted at a frame repetition rate of 8000 Hz, which results in an aggregate bit rate of 256 bits x 8000/sec = 2.048 Mbits/sec. The actual bit rate is 2.048 Mbit/s +/-50 ppm encoded in HDB3 (High Density Bipolar 3) format. Basic frames are divided into 32 timeslots numbered 0 to 31, see Figure 6. Each timeslot is 8 bits in length and is transmitted most significant bit first (numbered bit 1). This results in a single timeslot data rate of 8 bits x 8000/sec. = 64 kbit/s. It should be noted that the Zarlink ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit of an eight bit channel is numbered bit 7, see Figure 5. Therefore, ST-BUS bit 7 is synonymous with PCM30 bit 1; bit 6 with bit 2: and so on, see Zarlink Application Note MSAN-126 for more details on the ST-BUS. Tables 4 and 5 show the mapping between the ST-BUS channels and the PCM30 timeslots. When the device is in IMA (Inverse Mux for ATM) mode the mapping between the ST-BUS Channels and the PCM30 timeslots is according to Table 4. PCM30 timeslot 0 is reserved for basic frame alignment, CRC-4 multiframe alignment and the communication of maintenance information (facility data link). In most configurations timeslot 16 is reserved for either Channel Associated Signaling (CAS or ABCD bit signaling) or Common Channel Signaling (CCS). For V5.2 applications, timeslots 15, 16 and 31 may be used for CCS. The remaining timeslots are called channels and carry either PCM encoded voice signals or digital data. Channel alignment and bit numbering is consistent with timeslot alignment and bit numbering. However, channels are numbered 1 to 30 and relate to timeslots as per Table 6. PCM30 Timeslots 0 1 2 3 4 56789 10 11 12 13 14 15 ST-BUS Channels (DSTi/o and CSTi/o) 0 1 2 3 4 56789 10 11 12 13 14 15 PCM30 Timeslots 16 17 18 19 20 21 22 23 24252627282930 31 ST-BUS Channels (DSTi/o and CSTi/o) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 4 - ST-BUS Channel vs. PCM30 Timeslot for 2.048 Mbit/s DST/CST Streams (E1) PCM30 Timeslots 0 1 234 56 7 8 9 101112 13 14 15 ST-BUS F0/4 Chan(DSTi/o F1/5 and CSTi/o) F2/6 F3/7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 PCM30 Timeslots 1617181920 21 2223 24 25 26 27 28 29 30 31 ST-BUS F0/4 Chan(DSTi/o F1/5 and CSTi/o) F2/6 F3/7 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Table 5 - ST-BUS Channel vs. PCM30 Timeslot Relationship for 8.192 Mbit/s DST/CST Streams (E1) |
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