 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
MT9072AB датащи(PDF) 25 Page - Zarlink Semiconductor Inc |
|
|
|||||||||||||||||||||||||||||
MT9072AB датащи(HTML) 25 Page - Zarlink Semiconductor Inc |
|
|
25 / 275 page  MT9072 Data Sheet 25 Zarlink Semiconductor Inc. 6 26 46 66 86 106 126 146 D4 J2 N4 P6 P12 P14 K16 E14 TPOS[0] TPOS[1] TPOS[2] TPOS[3] TPOS[4] TPOS[5] TPOS[6] TPOS[7] O Transmit Positive. This pin is an output for the transmit side of the framer; it typically interfaces to an LIU. If used by itself it can provide single rail NRZ (Non Return to Zero) data. If TPOS is used in conjunction with TNEG it can provide dual rail NRZ data or dual rail RZ (Return to Zero) data. The clock at the TXCL pin is used to clock data out of the TPOS pin. Pins TPOS[0-7] are used for Framers[0-7] respectively. In T1 mode, line codes are selected with control bits: TZCS2-0, TPDV, TXB8ZS, RZNRZ and UNIBI (Address Y01). T1 mode is selected if the T1E0 bit (Address 900) is 1. In E1 mode, line codes are selected with control bits: COD0-1 and THDB3 (Address Y02). E1 mode is selected if the T1E0 bit (Address 900) is 0. 7 27 47 67 87 107 127 147 E1 J3 P1 P7 R9 P15 J13 E15 TNEG[0] TNEG[1] TNEG[2] TNEG[3] TNEG[4] TNEG[5] TNEG[6] TNEG[7] O Transmit Negative. This pin is an output for the transmit side of the framer; it typically interfaces to an LIU. TNEG is used in conjunction with TPOS to provide dual rail NRZ (Non Return to Zero) data or dual rail RZ (Return to Zero) data. The clock at the TXCL pin is used to clock data out of the TNEG pin. Pins TNEG[0-7] are used for Framers[0-7] respectively. In T1 mode, line codes are selected with control bits: TZCS2-0, TPDV, TXB8ZS, RZNRZ and UNIBI (Address Y01). T1 mode is selected if the T1E0 bit (Address 900) is 1. In E1 mode, line codes are selected with control bits: COD0-1 and THDB3 (Address Y02). E1 mode is selected if the T1E0 bit (Address 900) is 0. 8 28 48 68 88 108 132 148 E2 J4 P2 P8 R10 P16 J14 E16 TXCL[0] TXCL[1] TXCL[2] TXCL[3] TXCL[4] TXCL[5] TXCL[6] TXCL[7] IO 1.544/2.048 MHz Transmit Clock. This pin accepts/outputs a clock that is used to clock data out of the transmit side of the framer on pins TPOS and TNEG. If TPOS/TNEG are configured for RZ output then the rising edge of the clock is used to clock TPOS/TNEG data. If TPOS/TNEG are configured for NRZ output then either a rising or falling TxCL edge can be selected to clock TPOS/TNEG data. Pins TxCL[0-7] are used for Framers[0-7] respectively. In T1 mode this pin is an input. The 1.544 MHz transmit clock is typically provided by an external PLL (Phase Lock Loop) or LIU. An active rising or falling edge is selected with the CLKE bit (Address Y01). See Figure 52. In E1 mode this pin is an output. The 2.048 MHz transmit clock is synchronous with the 4.096 MHz ST-BUS clock input to pin CKi. An active rising or falling edge is selected with the T2OP bit (Address Y02). See Figure 71. Pin Description (continued) Pin # Name Type Description (see Notes 1 to 7) LQFP LBGA |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
