MT9072AB datasheet(65/275 Pages) ZARLINK

65 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

8.1.2

T1 Common Channel Signaling

One 64 Kbit/s channel can be mapped from/to an external multichannel HDLC using the CSTi/0 pins. This is

accomplished by writing to register Y0B and Y04(CSIGEN bit). Note that only channels 0 to 23 can be used on the

CSTi/o streams in Common Channel Signaling applications. For the CSTo stream only the channel that is selected

is driven, the rest of the stream is tristate. In 8 Mbit/s mode up to 4 channels per 8 Mbit/s CSTi/0 stream will be

assigned to the external HDLC in accordance with Table 2.

8.2

E1 Signaling

8.2.1

Channel Associated Signaling (CAS) Operation

The purpose of the CAS signaling Multiframing algorithm is to provide a scheme that will allow the association of a

specific ABCD signaling nibble with the appropriate PCM30 channel. The signaling nibble when sinked or sourced

from the ST-BUS will have the ABCD bits being bits 3 to 0 respectively.

A CAS signaling multiframe consists of 16 basic frames (numbered 0 to 15), which results in a multiframe repetition

rate of 2 msec. It should be noted that the boundaries of the signaling multiframe may be completely distinct from

those of the CRC-4 multiframe. CAS multiframe alignment is based on a multiframe alignment signal (a 0000 bit

sequence), which occurs in the most significant nibble of timeslot 16 of basic frame 0 of the CAS multiframe. Bits 5,

7 and 8 (usually designated X) are spare bits and are normally set to one if not used. Bit 6 of this timeslot is the

multiframe alarm bit (usually designated Y). When CAS multiframing is acquired on the receive side, the transmit

Address

Description

900

Global Control 0

CK1 determines an 8 Mhz stream or a 2 Mhz stream. STBUS selects a GCI

or ST-BUS CSTi, CSTo streams.

Y00

Framing Mode Select

The number of signaling bits available is dependent on the mode. For D4 and

T1DM 2 bits of signaling, for ESF 4 bits. In G.802 and IMA mode signaling is

not supported.

Y04

Signaling Control

Word

This register defines the selection between robbed bit or common channel,

signaling debounce and substitute bits C,D bits for D4 mode on CSTo. Y04

bit 0 and 1 are used to control the frequency of the signaling change

interrupt.

Y0B

Common Channel

signaling Map Register

This register is used to determine the CSTi/o channel to PCM24 timeslot

mapping for common channel signaling.

Y10

Synchronization and

Alarm Status Word

The receive signaling will not work if terminal frame synchronization and

multiframe synchronization is not achieved.

Y50-Y60 Per Channel Transmit

signaling

The clear channel bit can be used to block insertion of signaling in the

transmit direction. The MPST bit can be used to determine the source of the

transmit signaling, which is either the CSTi stream or the transmit signaling

ram.

Y35

Receive Line and

Timer Interrupt Status

The CASRI bit is set if unmasked and receive signaling changes on any

channel. The channels marked as clear channel do not generate an

interrupt.

Y45

Receive Line and

Timer Interrupt Mask

CASRIM is the mask bit for the Y35.

Table 22 - Registers Related to Signaling (T1)

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