MT9072AB datasheet(91/275 Pages) ZARLINK

91 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

14.1.5

T1 Mu-law Milliwatt

If the control bit ADSEQ is one (register address Y01), the Mu-law digital milliwatt sequence (Table 45) defined by

G.711, is available to be transmit on any combination of selected channels. The channels are selected by setting

the TTSTn control bit (register address Y90-YA7). The same sequence is available to replace received data on any

combination of DSTo channels. This is accomplished by setting the RRSTn control bit (register address Y90-YA7)

for the corresponding channel. Note that Bit 1 is the sign bit and is sent first.

14.1.6

T1 Alarms

The alarms shown in Table 46 are detected by the receiver. The status register bits provide real time status of the

alarm, while the interrupt status registers bits provide latched status indications which are cleared when read. Each

interrupt status register may also generate a maskable interrupt. The possible transmitted alarms are also shown in

the table. See the register bit descriptions for details.

PCM 24 Payload Data

Hex

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

001

111

000

101

000

101

001

111

001

111

000

101

000

101

001

111

Table 45 - Mu Law Digital Milliwatt Pattern (T1)

Control/Status Register

Interrupt Status

Description

Bit

Address

Bit

Address

D4 Yellow Alarm. This bit is set if bit position 2 of virtually every

DS0 channel is a zero for a period of 600 milliseconds. The alarm is

tolerant of errors by permitting up to 16 ones in a 48 millisecond

integration period. The alarm clears in 200 milliseconds after being

removed from the line.

D4YALM

Y10

D4YALMI

Y35

D4 Yellow Alarm - 48 millisecond sample. This bit is set if bit

position 2 of virtually every DS0 channel is a zero for a period of 48

milliseconds. The alarm is tolerant of errors by permitting up to 16

ones in the integration period. This bit is updated every 48

milliseconds.

D4Y48

Y10

D4Y48I

Y35

Table 46 - Alarm Control and Status Bits (T1)

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