MT9072AB datasheet(24/275 Pages) ZARLINK

24 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

Pin Description

Pin #

Name

Type

Description (see Notes 1 to 7)

LQFP

LBGA

1,21,41,61,

81,101,121,

141,161,

179

E7,E8,E9,

E10,E11,

M7,M8,M9,

M10,M11

VSS

Ground. 0VDC.

2,22,42,62,

82,102,122,

142,162,18

G5,H5,J5,

K5,L5,G12,

H12J12,K1

2,L12

VDD

Supply Voltage. +3.3 VDC nominal.

103

123

143

R15

K13

F15

RPOS[0]

RPOS[1]

RPOS[2]

RPOS[3]

RPOS[4]

RPOS[5]

RPOS[6]

RPOS[7]

Receive Positive. This pin is an input for the receive side of the

framer; it typically interfaces to an LIU. If used by itself it can accept

single rail NRZ (Non Return to Zero) data. If RPOS is used in

conjunction with RNEG it can accept dual rail NRZ data or dual rail RZ

(Return to Zero) data. The clock at the EXCLi pin is used to clock data

into the RPOS pin. Pins RPOS[0-7] are used for Framers[0-7]

respectively.

In T1 mode, transmit line codes are selected with control bits:

RZCS1-0, RXB8ZS, RZNRZ and UNIBI (Address Y01). T1 mode is

selected if the T1E0 bit (Address 900) is 1.

In E1 mode, line codes are selected with control bits: COD0-1 and

RHDB3 at (Address Y02). E1 mode is selected if the T1E0 bit

(Address 900) is 0.

104

124

144

P10

R16

K14

F16

RNEG[0]

RNEG[1]

RNEG[2]

RNEG[3]

RNEG[4]

RNEG[5]

RNEG[6]

RNEG[7]

Receive Negative. This pin is an input for the receive side of the

framer; it typically interfaces to an LIU. RNEG is used in conjunction

with RPOS to accept dual rail NRZ (Non Return to Zero) data or dual

rail RZ (Return to Zero) data. The clock at the EXCLi pin is used to

clock data into the RNEG pin. Pins RNEG[0-7] are used for

Framers[0-7] respectively.

In T1 mode, receive line codes are selected with control bits:

RZCS1-0, RXB8ZS, RZNRZ and UNIBI at (Address Y01). T1 mode is

selected if the T1E0 bit (Address 900) is 1.

In E1 mode, line codes are selected with control bits: COD0-1 and

RHDB3 at (Address Y02). E1 mode is selected if the T1E0 bit

(Address 900) is 0.

105

125

145

P11

P13

K15

E13

EXCLi(0)

EXCLi(1)

EXCLi(2)

EXCLi(3)

EXCLi(4)

EXCLi(5)

EXCLi(6)

EXCLi(7)

1.544/2.048 MHz Extracted Clock. The rising edge of the clock

applied at this input is used to clock RZ data into the receive side of

the framer on pins RPOS and RNEG. If RPOS/RNEG are configured

for NRZ input then either a rising or falling edge on the EXCLi clock

can be selected to clock RPOS/RNEG data. Pins EXCLi[0-7] are used

for Framers[0-7] respectively.

In T1 mode, this pin accepts a 1.544 MHz extracted clock. An active

rising or falling edge is selected with the CLKE bit (Address Y01). See

Figure 53.

In E1 mode, this pin accepts a 2.048 MHz extracted clock. An active

rising or falling edge is selected with the CLKE bit (Address Y02). See

Figure 73.

MT9072AB датащи(PDF) 24 Page - Zarlink Semiconductor Inc

MT9072AB датащи(HTML) 24 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL