MT9072AB datasheet(74/275 Pages) ZARLINK

74 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

• Packets which are at least 26 bits in length but less than 32 bits between the flags are also invalid. In this

case the data is written to the FIFO but the last byte is tagged with a “bad packet” indication.

• If a frame abort sequence is detected the packet is invalid. Some or all of the current packet will reside in the

receive FIFO, assuming the packet length before the abort sequence was at least 25 bits long.

9.1.4

Frame Abort

The transmitter will abort a current packet by substituting a zero followed by seven contiguous 1s in place of the

normal packet. The receiver will abort upon reception of seven contiguous 1s occurring between the flags of a

packet which contains at least 25 bits.

Note that should the last received byte before the frame abort end with contiguous 1s, these are included in the

seven 1s required for a receiver abort. This means that the location of the abort sequence in the receiver may occur

before the location of the abort sequence in the originally transmitted packet. If this happens then the last data

written to the receive FIFO will not correspond exactly with the last byte sent before the frame abort.

9.1.5

Interframe Time Fill and Link Channel States

When the HDLC transmitter is not sending packets it will wait in one of two states

• Interframe Time Fill state: This is a continuous series of flags occurring between frames indicating that the

channel is active but that no data is being sent.

• Idle state: An idle Channel occurs when at least 15 contiguous 1s are transmitted or received.

In both states the transmitter will exit the wait state when data is loaded into the transmitter FIFO.

9.1.6

Go-Ahead

A go ahead is defined as the pattern "011111110" (contiguous 7Fs) and is the occurrence of a frame abort sequence

followed by a zero, outside of the boundaries of a normal packet. Being able to distinguish a proper (in packet)

frame abort sequence from one occurring outside of a packet allows a higher level of signaling protocol which is not

part of the HDLC specifications.

9.1.7

Functional Description

The HDLC transceiver can be reset by either the power reset input signal or by the HRST Control bit in the HDLC

Test control register (YF3). When reset, the HDLC Control Registers are cleared, resulting in the transmitter and

receiver being disabled. The Receiver and Transmitter can be enabled independent of one another through HDLC

control(YF2 bits RXEN and TXEN). The transceiver input and output are enabled when the enable control bits in

HDLC control are set. Transmit to receive loopback as well as a receive to transmit loopback are also supported.

Transmit and receive bit rates and enables can operate independently.

Received packets from the serial interface, are sectioned into bytes by an HDLC receiver that detects flags, checks

for go-ahead signals, removes inserted zeros, performs a cyclical redundancy check (CRC) on incoming data, and

monitors the address if required. Packet reception begins upon detection of an opening flag. The resulting bytes are

concatenated with two status bits (RQ9, RQ8 in HDLC status register Y1D) and placed in a receiver first-in-first-out

(Rx FIFO); a buffer register that generates status and interrupts for microprocessor read control.

In conjunction with the control circuitry, the microprocessor writes data bytes into a Tx buffer register (Tx FIFO) that

generates status and interrupts. Packet transmission begins when the microprocessor writes a byte to the Tx FIFO.

Two status bits are added to the Tx FIFO for transmitter control of frame aborts (FA) and end of packet (EOP) flags.

Packets have flags appended, zeros inserted, and a CRC, also referred to as frame checking sequence (FCS),

added automatically during serial transmission. When the Tx FIFO is empty and finished sending a packet,

Interframe Time Fill bytes (continuous flags (7E hex)), or Mark Idle (continuous ones) are transmitted to indicate

that the channel is idle.

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