MT9072AB datasheet(81/275 Pages) ZARLINK

81 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

10.1.5.2

Transmit AIS Operation (TAIS Pin)

The TAIS pin allows all eight framers of the MT9072 to transmit an all ones signal (AIS) at the TPOS and TNEG

output pins from the point of power-up, without the need to write any control registers. During this time the IRQ pin

is in a high impedance state. After the interface has been initialized normal operation can take place by making

TAIS high.

10.1.5.3

IEEE 1149.1-1990 Test Access Port (TAP)

Five signals (TDI, TDO, TMS, TCK & TRST) make up the Test Access Port (TAP) of the IEEE 1149.1-1990

Standard Test Port and Boundary-Scan Architecture. The TAP provides access to test support functions built into

the MT9072. The TAP is also referred to as a JTAG (Joint Test Action Group) port. See the JTAG section for

additional details.

10.1.6

Data Link (DL) Interface (RxDL, RxDLC, TxDL, TxDLC Pins)

Dedicated data link pins are included which provide the user the option of bypassing the receive elastic buffer and

accessing timeslot 0 data link (DL) data with an external controller. The MT9072 provides numerous additional

methods for accessing the DL, refer to the DL sections for details.

Function

Status

Control Bits

Mode

Termination

RxTRS=0, TxTRS=0

Y03

Loopbacks

Deactivated

DLBK,RLBK,SLBK,PLBK=0

RTSL(n), LTSL(n)=0

Y01

Y90-YAF

Transmit FAS

Cn0011011

CSYN=0

Y00

Transmit non-FAS

1/Sn1111111

Y03

Transmit MFAS (CAS)

00001111

TMA1,2,3,4=0

X1,Y,X2,X3=1

Y05

Data Link Pin

Deactivated

Sa4SS1-0,Sa5SS1-0,Sa6SS1-0,Sa

7SS1-0,Sa8SS1-0=0

Y08

CRC Interworking

Activated

AUTC=0

Y00

Signaling

CAS ST-BUS Source

CSIG=0

CASS(n)=0

Y03

Y50-Y6F

ABCD Bit Debounce

Deactivated

DBNCE=0

Y05

Interrupts

All Unmasked

Suspended

ALL MASK BITS =0

SPND=0, INTA=0

Y40-Y43

Y02

RxMF Output

signaling Multiframe

MFSEL=0

Y02

Error Insertion

Deactivated

E1, E2, BPVE,CRCE,FASE,

NFSE,LOSE,PERR=0

Y01

Counters

Cleared

ALL BITS =0

Y15-Y1A

Counter Latches

Cleared

ALL BITS =0

Y28-Y2B

Per Timeslot Control

Buffer

All locations cleared

ALL BITS =0

Y90-YAF

All Other Control

Registers

All locations cleared

ALL BITS =0

All Other Control

Table 37 - Reset Status (E1)

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