M16CSLASH26 datasheet(206/239 Pages) RENESAS

206 / 239 page

Renesas Technology Corp.

CPU Rewrite Mode (Flash Memory Version)

200

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Status Register

The status register shows the operating state of the flash memory and whether erase operations and

programs ended successfully or in error. It can be read only in the EW0 mode, in the following ways. The

status cannot be read out in the EW1 mode and during suspend.

(1) By reading an arbitrary even address from the user ROM area after writing the read status register

command (7016)

(2) By reading an arbitrary even address from the user ROM area in the period from when the program

starts or erase operation starts to when the read array command (FF16) is input

Table 1.20.2 shows the status register.

In the EW1 mode, the status corresponding to the below is stored in the flash memory control register 0.

Read this register for status check.

Also, the status register can be cleared in the following way.

(1) By writing the clear status register command (5016)

After a reset, the status register is set to “8016”.

Each bit in this register is explained below.

Sequencer status (SR7) / FMR00

After power-on, the sequencer status is set to 1(ready).

The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy)

during write or erase operation and is set to “1” upon completion of these operations.

Erase status (SR5) / FMR07

The erase status informs the operating status of erase operation to the CPU. When an erase error

occurs, it is set to “1”.

The erase status is reset to “0” when cleared.

Program status (SR4)

The program status informs the operating status of write operation to the CPU. When a write error

occurs, it is set to “1”.

The program status is reset to “0” when cleared.

When an erase command is in error (which occurs if the command entered after the block erase

command (2016) is not the confirmation command (D016), both the program status and erase status

(SR5) are set to “1”.

When the program status or erase status =“1”, only the following flash commands will be accepted:

Read Array, Read Status Register, and Clear Status Register.

Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):

(1) When the valid command is not entered correctly

(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase

(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is

entered, read array is assumed and the command that has been set up in the first bus cycle is

canceled.

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