M16CSLASH26 datasheet(48/239 Pages) RENESAS

48 / 239 page

Renesas Technology Corp.

Power Control

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Figure 1.8.8. State transition diagram of power control mode

Transition of stop mode, wait mode

Transition of normal mode

Interrupt

CM10=1

CM03="1"

All oscillators stopped

Stop mode

All oscillators stopped

Stop mode

All oscillators stopped

Medium-speed mode

(divided-by-8 mode)

Reset

High-speed/medium-

speed mode

Low-speed/low power

dissipation mode

Wait mode

CPU operation stopped

Interrupt

WAIT

instruction

(Note 1)

Interrupt

WAIT

instruction

Interrupt

WAIT

instruction

Normal mode

(Refer to the following for the transition of normal mode.)

When

low-speed

mode

When

low powe

dissipation

mode

Medium-speed mode

(divided-by-8 mode)

Main clock is oscillating

Sub clock is stopped

High-speed mode

Medium-speed mode

(divided-by-2 mode)

BCLK : f(XIN)/8

CM07 = 0 CM06 = 1

High-speed mode

BCLK : f(XIN)/2

CM07 = 0 CM06 = 0

CM17 = 0 CM16 = 1

Medium-speed mode

(divided-by-2 mode)

BCLK : f(XIN)/16

CM07 = 0 CM06 = 0

CM17 = 1 CM16 = 1

Medium-speed mode

(divided-by-16 mode)

BCLK : f(XIN)/4

CM07 = 0 CM06 = 0

CM17 = 1 CM16 = 0

Medium-speed mode

(divided-by-4 mode)

BCLK : f(XIN)

CM07 = 0

CM17 = 0 CM16 = 0

Medium-speed mode

(divided-by-8 mode)

BCLK : f(XIN)/8

CM07 = 0

CM06 = 1

BCLK : f(XIN)/16

CM07 = 0 CM06 = 0

CM17 = 1 CM16 = 1

BCLK : f(XIN)/4

CM07 = 0 CM06 = 0

CM17 = 1 CM16 = 0

Medium-speed mode

(divided-by-16 mode)

Medium-speed mode

(divided-by-4 mode)

BCLK : f(XIN)/2

CM07 = 0 CM06 = 0

CM17 = 0 CM16 = 1

BCLK : f(XIN)

CM07 = 0 CM06 = 0

CM17 = 0 CM16 = 0

BCLK : f(XCIN)

CM07 = 1 , CM06 = 1

CM15 = 1

BCLK : f(XCIN)

CM07 = 1

CM07 = 0

(Note 3, 5)

CM07 = 0 (Note 3)

CM06 = 1

CM04 = 0

CM07 = 1

(Note 4)

CM07 = 0 (Note 3)

CM06 = 0 (Note 5)

CM04 = 1

CM07 = 1 (Note 4)

CM05 = 1

CM05 = 0

CM05 = 1

Main clock is oscillating

Sub clock is stopped

CM04 = 0

CM04 = 1

CM06 = 0

(Notes 3, 5)

CM06 = 1

CM04 = 0

CM04 = 1

(Notes 3, 5)

Note 3: Switch clock after oscillation of main clock is sufficiently stable.

Note 4: Switch clock after oscillation of sub clock is sufficiently stable.

Note 5: Change CM06 after changing CM17 and CM16.

Low-speed mode

Main clock is oscillating

Sub clock is oscillating

Main clock is stopped

Sub clock is oscillating

Low power

dissipation mode

Main clock is oscillating

Sub clock is oscillating

CM10=1

CM06 =

Stop mode

Ring oscillator, Ring oscillator

dissipation mode

Interrupt

(Note 2)

CM10=1

Wait mode

Interrupt

WAIT

instruction

(Note 1)

Note 1: When bit PM21 = "0" (system clock protective function unused).

Note 2: The ring oscillator clock divided by 8 provides BCLK.

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