M16CSLASH26 datasheet(69/239 Pages) RENESAS

69 / 239 page

Precautions for Interrupts

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP

FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted

before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the

interrupt control register is rewritten due to effects of the instruction queue.

• When the polarity of the INT0 , INT1, INT3 through INT5 pins is changed, the interrupt request bit is

sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 1.9.13

shows the procedure for changing the INT interrupt generate factor.

(5) Watchdog timer interrupt

• Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog

timer).

(6) Rewrite the interrupt control register

• To rewrite the interrupt control register, do so at a point where an interrupt request for that register is not

generated. If there is possibility of the interrupt request occur, disable the interrupt before rewriting the

interrupt control register. Some program examples are described as follow:

When changing an interrupt control register with interrupts enabled, please read the following precau-

tions on instructions used before changing the register.

(1) Changing a non-interrupt request bit

If an interrupt request for an interrupt control register is generated during an instruction to rewrite the

interrupt is ignored. This will depend on the instruction. If this creates problems, use the instructions

below to change the register.

Instructions : AND, OR, BCLR, BSET

(2) Changing the interrupt request bit

When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit

is not cleared sometimes. This will depend on the instruction. If this creates problems, use the instruc-

tions below to change the register.

Instructions : MOV

M16C/26 датащи(PDF) 69 Page - Renesas Technology Corp

M16C/26 датащи(HTML) 69 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL