M16CSLASH26 datasheet(52/239 Pages) RENESAS

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Interrupts

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.

(1) Special interrupts

Special interrupts are non-maskable interrupts.

• Reset

Reset occurs if an “L” is input to the RESET pin.

• NMI interrupt

If enabled, an NMI interrupt occurs if an “L” is input to the NMI pin.

• DBC interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances.

• Watchdog timer interrupt

Generated by the watchdog timer. Write to the watchdog timer start register after the watchdog timer

interrupt occurs (initialize watchdog timer).

• Single-step interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug

flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.

• Address match interrupt

An address match interrupt occurs immediately before the instruction held in the address indicated by

the address match interrupt register is executed with the address match interrupt enable bit set to “1”.

If an address other than the first address of the instruction in the address match interrupt register is set,

no address match interrupt occurs.

(2) Peripheral I/O interrupts

A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-

tions are dependent on classes of products, so the interrupt factors too are dependent on classes of

products. The interrupt vector table is the same as the one for software interrupt numbers 0 through

31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.

• Bus collision detection interrupt

This is an interrupt that UART2 generates.

• DMA0 interrupt, DMA1 interrupt

These are interrupts that DMA generates.

• Key-input interrupt

A key-input interrupt occurs if an “L” is input to the KI pin.

• A-D conversion interrupt

This is an interrupt that the A-D converter generates.

• UART0, UART1, and UART2/NACK2 transmission interrupt

These are interrupts that the serial I/O transmission generates.

• UART0, UART1, and UART2/ACK2 reception interrupt

These are interrupts that the serial I/O reception generates.

• Timer A0 interrupt through timer A4 interrupt

These are interrupts that timer A generates

• Timer B0 interrupt through timer B2 interrupt

These are interrupts that timer B generates.

• INT0, INT1, INT3 through INT5 interrupt

An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.

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