M16CSLASH26 datasheet(59/239 Pages) RENESAS

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Interrupts

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Interrupt Sequence

This section describes an interrupt sequence — what are performed over a period from the time an inter-

rupt is accepted until the time the interrupt routine is executed .

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

In the interrupt sequence, the processor operates in the following sequence:

(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address

0000016. After this, the corresponding interrupt request bit becomes “0”.

(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence

in the temporary register (Note) within the CPU.

(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to

“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63,

is executed)

(4) Saves the content of the temporary register (Note) within the CPU in the stack area.

(5) Saves the content of the program counter (PC) in the stack area.

(6) Sets the interrupt priority level of the accepted instruction in the IPL.

After the interrupt sequence is completed, the processor resumes executing instructions from the first

address of the interrupt routine.

Note: This register cannot be utilized by the user.

Interrupt Response Time

'Interrupt response time' is the period between the time an interrupt occurs and the time the first instruc-

tion within the interrupt routine has been executed. This time comprises the period from the occurrence

of an interrupt to the completion of the instruction under execution at that moment (a) and the time

required for executing the interrupt sequence (b). Figure 1.9.4 shows the interrupt response time.

Figure 1.9.4. Interrupt response time

Instruction

Interrupt sequence

Instruction in

interrupt routine

Time

Interrupt response time

(a)

(b)

Interrupt request acknowledged

Interrupt request generated

(a) Time from interrupt request is generated to when the instruction then under execution is completed.

(b) Time in which the instruction sequence is executed.

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