M16CSLASH26 datasheet(67/239 Pages) RENESAS

67 / 239 page

Interrupts

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents

match the program counter value. Four address match interrupts can be set, each of which can be enabled

and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the

interrupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the

value of the program counter (PC) that is saved to the stack area varies depending on the instruction being

executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot

be used for external area.

Figure 1.9.12 shows the address match interrupt-related registers.

Bit name

Bit symbol

Symbol

Address

When reset

AIER

000916

XXXXXX002

Address match interrupt enable register

Function

Address match interrupt 0

enable bit

0 : Interrupt disabled

1 : Interrupt enabled

AIER0

Address match interrupt 1

enable bit

AIER1

Symbol

Address

When reset

RMAD0

001216 to 001016

X0000016

RMAD1

001616 to 001416

X0000016

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to

be indeterminated.

Address setting register for address match interrupt

Function

Values that can be set

Address match interrupt register i (i = 0, 1)

0000016 to FFFFF16

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to

be indeterminated.

0 : Interrupt disabled

1 : Interrupt enabled

b0 b7

(b19)

(b16)

(b15)

(b8)

(b23)

Figure 1.9.12. Address match interrupt-related registers

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