M16CSLASH26 datasheet(62/239 Pages) RENESAS

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Renesas Technology Corp.

Interrupts

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Figure 1.9.7. Operation of saving registers

The operation of saving registers carried out in the interrupt sequence is dependent on whether the

content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If

the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the

program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at

a time. Figure 1.9.7 shows the operation of the saving registers.

Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer

indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).

(2) Stack pointer (SP) contains odd number

[SP]

(Odd)

Address

Sequence in which order

registers are saved

(2)

(1)

Finished saving registers

in four operations.

(3)

(4)

(1) Stack pointer (SP) contains even number

Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

Address

Program counter (PCM)

Stack area

Flag register (FLGL)

Program counter (PCL)

Sequence in which order

registers are saved

(2) Saved simultaneously,

all 16 bits

(1) Saved simultaneously,

all 16 bits

Finished saving registers

in two operations.

Program counter (PCM)

Stack area

Flag register (FLGL)

Program counter (PCL)

Saved simultaneously,

all 8 bits

Flag register

(FLGH)

Program

counter (PCH)

Flag register

(FLGH)

Program

counter (PCH)

[SP] - 5 (Even)

[SP] - 4 (Odd)

[SP] - 3 (Even)

[SP] - 2 (Odd)

[SP] - 1 (Even)

[SP]

(Even)

[SP] - 5 (Odd)

[SP] - 4 (Even)

[SP] - 3 (Odd)

[SP] - 2 (Even)

[SP] - 1 (Odd)

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