M16CSLASH26 datasheet(15/239 Pages) RENESAS

15 / 239 page

Renesas Technology Corp.

CPU

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Figure 1.4.2. Seven of these registers (R0, R1, R2, R3, A0,

A1, and FB) come in two sets; therefore, these have two register banks.

(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and

arithmetic/logic operations.

Registers R0 and R1 can each be used as dual 8-bit data registers. As such, their high-order bytes are

designated R0H/R1H, while their low-order bytes become R0L/R1L, respectively. In some instructions,

registers R2 and R0, as well as R3 and R1, can be combined to serve as 32-bit data registers (R2R0/R3R1).

(2) Address registers (A0 and A1)

Address registers (A0 and A1) consist of 16 bits each. Individually, they can be used for three types of

are also used for transfer and arithmetic/logic operations, as well as three special instruction addressing

modes: address register relative with 20-bit displacement, 32-bit address register indirect, and 32-bit

b15

R0(Note)

b15

R1(Note)

R2(Note)

b15

R3(Note)

b15

A0(Note)

b15

A1(Note)

b15

FB(Note)

b15

Data

registers

Address

registers

Frame base

registers

b15

b19

Program counter

Interrupt table

User stack pointer

Interrupt stack

pointer

Static base

Flag register

INTB

USP

ISP

FLG

Note: These registers consist of two register banks.

Figure 1.4.2. Central processing unit register

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