M16CSLASH26 datasheet(58/239 Pages) RENESAS

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Interrupts

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP

FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted

before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the

interrupt control register is rewritten due to effects of the instruction queue.

Rewrite the interrupt control register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for

that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after

the interrupt is disabled. The program examples are described as follow:

When changing an interrupt control register at a point where the interrupt is disabled, please read the

following precautions on instructions used before changing the register.

(1) Changing a non-interrupt request bit (interrupt priority level)

If an interrupt request for an interrupt control register is generated during an instruction to rewrite the

consequently the interrupt is ignored. This will depend on the instruction used. If this creates problems,

use the instructions below to change the register.

Instructions : AND, OR, BCLR, BSET

(2) Changing the interrupt request bit

When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit

is not cleared sometimes. This will depend on the instruction used. If this creates problems, use the

instructions below to change the register.

Instructions : MOV

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