M16CSLASH26 datasheet(68/239 Pages) RENESAS

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Renesas Technology Corp.

Precautions for Interrupts

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Set the interrupt priority level to level 0

(Disable INTi interrupt)

Set the polarity select bit

Set the interrupt priority level to level 1 to 7

(Enable the accepting of INTi interrupt request)

Clear the interrupt enable flag to 0

(Disable interrupt)

Set the interrupt enable flag to 1

(Enable interrupt)

Note: Execute the setting above individually. Don't execute two or

more settings at once(by one instruction).

Clear the interrupt request bit to 0

Precautions for Interrupts

(1) Reading address 0000016

• Do not read address 0000016 by software.

When a maskable interrupt is generated, the CPU reads the interrupt information (the interrupt number

and interrupt request level) in the interrupt sequence. The interrupt request bit of this interrupt is written

in address 0000016. Therefore, reading 0000016 may cancel the interrupt or generate an unexpected

one.

(2) Setting the stack pointer

• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt

before setting a value in the stack pointer may cause a runaway program. Be sure to set a value in the

stack pointer before accepting an interrupt.

When using the NMI interrupt, initialize the stack pointer at the beginning of the program. Concerning the

first instruction immediately after reset, the generation of any interrupts, including the NMI interrupt, is

prohibited.

(3) The NMI interrupt

•The NMI interrupt is enabled or disabled in bit4 of the processor mode register 2. It is disabled by

default (the pin is used as P85)after reset. Once enabled, it stays enabled until a reset is applied.

• The NMI interrupt input level can be determined by reading the contents of the P8 register.

• If NMI is enabled, do not attempt to go into stop mode with the NMI input in the “L” state. With the NMI

input in the “L” state, the CM10 is fixed to “0”, therefore, any attempt to go into stop mode is turned

down.

• If NMI is enabled, going into wait mode with the NMI input in the “L” state does not reduce the power

consumption. With the NMI input in the “L” state, the CPU stops but the oscillation is not stop, so

power consumption is not reduced. Having NMI in "L" state when going into a wait mode may also

cause an unpredictable behavior of the program.

• Signal input to the NMI pin require an “L” level of '2 cycles of BCLK + 300ns' or more.

(4) External interrupt

• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0

, INT1, INT3 through INT5 regardless of the CPU operation clock.

Figure 1.9.13. Switching condition of INT interrupt request

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