M16CSLASH26 datasheet(77/239 Pages) RENESAS

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DMAC

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

(1) Transfer cycle

The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area

(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination

write). The number of read and write bus cycles depends on the source and destination addresses. Also,

the bus cycle itself is longer when software waits are inserted.

(a) Effect of source and destination addresses

When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd

addresses, there are one more source read cycle and destination write cycle than when the source

and destination both start at even addresses.

(b) Effect of software wait

When the SFR area or a memory area with a software wait is accessed, the number of cycles is

increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.

Figure 1.11.5 shows the example of the transfer cycles for a source read. For convenience, the destina-

tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.

In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the

transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-

tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure

1.11.5, if 16-bit data is being transferred from an odd source address to an odd destination address, two

bus cycles are required for both the source read cycle and the destination write cycle.

(2) DMAC transfer cycles

Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the

number of DMAC transfer cycles.

The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

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