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M16C/26 датащи(PDF) 60 Page - Renesas Technology Corp |
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M16C/26 датащи(HTML) 60 Page - Renesas Technology Corp |
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60 / 239 page ![]() Renesas Technology Corp. Interrupts 54 M16C/26 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Under development Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Indeterminate 1 2 34 56 78 9 10 11 12 13 1415 16 1718 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2 contents SP-4 contents vec contents vec+2 contents Interrupt information Address 0000 Indeterminate SP-2 SP-4 vec vec+2 PC BCLK Address bus Data bus W R Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 1.9.6 is set in the IPL. Shown in Table 1.9.6 are the IPL values of software and special interrupts when they are accepted. Table 1.9.6. Relationship between interrupts without interrupt priority levels and IPL Stack pointer (SP) value Interrupt vector address 6-Bit bus, without wait 8-Bit bus, without wait Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Table 1.9.5. Time required for executing the interrupt sequence Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.9.5. Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure 1.9.5. Time required for executing the interrupt sequence Interrupt sources without priority levels Level that is set to IPL Watchdog timer, NMI, Oscillation stop and re-oscillation detection, VDET4 detection Software, address match, DBC, single-step 7 Not changed |
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