M16CSLASH26 datasheet(24/239 Pages) RENESAS

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Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Voltage detection circuit

A VDET4 detection interrupt request is generated when the input voltage of the VCC pin rises over

VDET4 or drops under VDET4 while the D40 bit of the D4INT register is equal to “1” (VDET4 detection

interrupt enabled). The VDET4 detection interrupt shares the interrupt vector with the watchdog

timer and oscillation stop detection interrupts.

To use the VDET4 detection interrupt as a way to get out of stop mode, set D41 bit of the D4INT

D42 bit of the the D4INT register is set to “1” when an input voltage over or under VDET4 is de-

tected. A VDET4 detection interrupt is generated when the D42 bit changes state from “0” to “1”.

The D42 bit needs to be cleared to “0" in the program. However, while in stop mode, if the input

voltage goes over VDET4 when the D41 bit is equal to “1”, a VDET4 detection interrupt is generated

regardless of the value of D42, which causes the microcomputer to get out of stop mode.

Table 1.5.2 shows the conditions under which a VDET4 detection interrupt request is generated.

The sampling clock, used for detecting when the input voltage goes over or under VDET4, is set

using the DF1 and DF0 bits of the D4INT register. Table 1.5.3 shows the sampling clock periods.

Precautions

1. Limitations on stop mode

With the VC13 bit of the VCR1 register equal to “1” (VCC

³ VDET4), VC27 bit of the VCR2 register

equal to “1” (VDET4 detection circuit enabled), and D40 bit of the D4INT register equal to “1” (VDET4

detection interrupt enabled), if the CM10 bit of the CM1 register is set to “1” (stop mode), a VDET4

detection interrupt is immediately generated, causing the microcomputer to get out of stop mode.

In systems where the microcomputer enters the stop mode when the input voltage in the VCC pin

drops under VDET4 and exits from stop mode when the input voltage goes over VDET4, ensure that

the CM10 bit is set to “1” when VC13 = “0” (VCC < VDET4)

Table 1.5.2. VDET4 detection interrupt request generation conditions

Table 1.5.3. Sampling clock periods

VC27 bit

Normal

operation

mode (Note 1)

0 to 1

Stop mode

(Note 4)

Wait mode

(Note 4)

operation mode

D40 bit

D41 bit

D42 bit

CM02 bit

VC13 bit

0 to 1

0 to 1 (Note 3)

1 to 0 (Note 3)

0 to 1 (Note 3)

1 to 0 (Note 3)

0 to 1

(Note 2)

Note 1: The status is handled as normal mode when not in wait or stop modes. (Refer to "Clock

Generating Circuit".)

Note 2: "

" implies either "0" or "1".

Note 3: An interrupt request for voltage reduction is generated a sampling time after the value of

the VC13 bit has changed. Refer to Figure 1.5.9 "VDET4 detection interrupt generation circuit

operation example" for details.

Note 4: Refer to "Limitations on stop mode", "Limitations on wait instructions with peripheral clocks

turned off".

DF1 to DF0=10

(BCLK divided by 32)

BCLK

(MHz)

Sampling time (µs)

3.0

6.0

12.0

24.0

DF1 to DF0=00

(BCLK divided by 8)

DF1 to DF0=01

(BCLK divided by 16)

DF1 to DF0=11

(BCLK divided by 64)

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