M16CSLASH26 datasheet(57/239 Pages) RENESAS

57 / 239 page

Interrupts

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Interrupt Enable Flag (I flag)

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this

flag to “1” enables all maskable interrupts while setting it to “0” disables all maskable interrupts. This flag

is set to “0” after reset.

Interrupt Request Bit

The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is

accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The

interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”).

Table 1.9.4. Interrupt levels enabled according

to the contents of the IPL

Table 1.9.3. Settings of interrupt priority levels

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

b2 b1 b0

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL2 IPL1 IPL0

IPL

Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits

of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared

with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.

Therefore, setting the interrupt priority level to “0” disables the interrupt.

Table 1.9.3 shows the settings of interrupt priority levels and Table 1.9.4 shows the interrupt levels

enabled, according to the contents of the IPL.

The following are conditions under which an interrupt is accepted:

· interrupt enable flag (I flag) = “1”

· interrupt request bit = “1”

· interrupt priority level > IPL

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are

independent, and so, not affected by one another.

M16C/26 датащи(PDF) 57 Page - Renesas Technology Corp

M16C/26 датащи(HTML) 57 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL