M16CSLASH26 datasheet(14/239 Pages) RENESAS

14 / 239 page

Renesas Technology Corp.

Memory

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Figure 1.4.1. Memory map

Functional Block Operation

The M16C/26 group accommodates certain units in a single chip. These units include ROM and

RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/

logic operations. Also included are peripheral units such as timers, serial I/O, A-D converter, and

I/O ports.

Memory

Figure 1.4.1 is a memory map of the M16C/26 group. The linear address space of 1M bytes extends

from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30262F4, there

is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the

reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is

stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the

internal register (INTB). See the section on interrupts for details.

From 0040016 up is RAM. For example, in the M30262F4, 1K bytes of internal RAM is mapped to the

space from 0040016 to 07FF16. In addition to storing data, the RAM also stores the stack used when

calling subroutines and when interrupts are generated.

These devices also contain two blocks of Flash ROM as Virtual EEPROM memory to store data. These

2 blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions.

The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for

peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR

area that is not occupied is reserved and cannot be used for other purposes.

SFR area

Internal RAM area

RESERVED

Virtual EEPROM

RESERVED

Flash ROM

Special Page

Vector Table

Undefined Instruction

Overflow

Break Instruction

Address Match

Single Step

Watchdog Timer

DBC

NMI

Reset

Hardware

Vectors

FFE00

FFFDC

FFFFF

YYYYY

10000

0F000

0F800

XXXXX

00400

00000

Ty pe N o .

A dd r e s s XX XX X

A d d r e s s YYYYY

M 3 02 62 F3G P

00 7FF

FA 0 0 0

M 3 02 62 F4G P

00 7FF

F8 00 0

M 3 02 62 F6G P

0 0 BFF

F4 00 0

M 3 02 62 F8G P

0 0 BFF

F0 00 0

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