M16CSLASH26 datasheet(130/239 Pages) RENESAS

130 / 239 page

Renesas Technology Corp.

Clock Synchronous Serial I/O Mode

124

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Figure 1.15.12. Typical transmit/receive timings in clock synchronous serial I/O mode

• Example of transmit timing (when internal clock is selected)

D0 D1 D2 D3 D4 D5 D6 D7

TCLK

Stopped pulsing because transfer enable bit = 0

Data is set in UARTi transmit buffer register

Tc = TCLK = 2(n + 1) / fi

fi: frequency of BRGi count source (f1, f8, f32)

n: value set to BRGi

Transfer clock

Transmit enable

bit (TE)

Transmit buffer

empty flag (Tl)

CLKi

TxDi

Transmit

flag (TXEPT)

CTSi

The above timing applies to the following settings:

* Internal clock is selected.

* CTS function is selected.

* CLK polarity select bit = 0 .

* Transmit interrupt cause select bit = 0 .

Transmit interrupt

request bit (IR)

Stopped pulsing because CTS = H

Transferred from UARTi transmit buffer register to UARTi transmit register

Shown in ( ) are bit symbols.

Cleared to 0 when interrupt request is accepted, or cleared by software

1 / fEXT

Dummy data is set in UARTi transmit buffer register

Transmit enable

bit (TE)

Transmit buffer

empty flag (Tl)

CLKi

RxDi

Receive complete

flag (Rl)

RTSi

Receive enable

bit (RE)

Receive data is taken in

Transferred from UARTi transmit buffer register to UARTi transmit register

Read out from UARTi receive buffer register

The above timing applies to the following settings:

* External clock is selected.

* RTS function is selected.

* CLK polarity select bit = 0 .

fEXT: frequency of external clock

Transferred from UARTi receive register

to UARTi receive buffer register

Receive interrupt

request bit (IR)

D1 D2

D4 D5

D1 D2

D3 D4

Shown in ( ) are bit symbols.

Meet the following conditions are met when the CLK

input before data reception = H

* Transmit enable bit

* Receive enable bit

* Dummy data write to UARTi transmit buffer register

Cleared to 0 when interrupt request is accepted, or cleared by software

Even if the reception is completed, RTS do not assert,

and it is asserted by readout of receive buffer register.

• Example of receive timing (when external clock is selected)

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