M16CSLASH26 datasheet(134/239 Pages) RENESAS

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Clock Asynchronous Serial I/O (UART) Mode

128

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Item

Specification

Transfer data format

• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit

• Parity bit: Odd, even, or nothing as selected

• Stop bit: 1 bit or 2 bits as selected

Transfer clock

• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :

fi/16 (n+1) (Note 1)

• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 =“1”) :

fEXT/16(n+1) (Note 1) (Note 2)

Transmission/reception control

• CTS function, RTS function, CTS and RTS function disabled: selectable

Transmission start condition

• To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”

- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”

- When CTS function selected, CTS input level = “L”

Reception start condition

• To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”

- Start bit detection

Interrupt request

• When transmitting

generation timing

- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at

address 037D16) = “0”: Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at

address 037D16) = “1”: Interrupts requested when data transmission from

UARTi transfer register is completed

•

When receiving

- Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

• Overrun error (Note 3)

Generated 6.5, 7, or 8.5 clock periods after the device started receiving the

next data before reading out the contents of the UARTi receive buffer register.

• Framing error

This error occurs when the number of stop bits set is not detected

• Parity error

This error occurs when if parity is enabled, the number of 1’s in parity and

character bits does not match the number of 1’s set

• Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is

encountered

Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and

transfer data format. Tables 1.15.7 and 1.15.8 list the specifications of the UART mode. Figure

1.15.18 shows the UARTi transmit/receive mode register.

Table 1.15.7. Specifications of UART Mode (1)

Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.

Note 2: fEXT is input from the CLKi pin.

Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit does not change.

fi = f1SIO, f2SIO, f8SIO, f32SIO

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