M16CSLASH26 datasheet(132/239 Pages) RENESAS

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Clock Synchronous Serial I/O Mode

126

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

This function allows the setting two transfer clock output pins and choosing one of the two to output a

clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.15.15.)

The multiple pins function is valid only when the internal clock is selected for UART1.

Figure 1.15.15. The transfer clock output from the multiple pins function usage

Microcomputer

TXD1 (P67)

CLKS1 (P64)

CLK1 (P65)

CLK

Note: This applies when the internal clock is selected and transmission

is performed only in clock synchronous serial I/O mode.

(d) Continuous receive mode

If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is

set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register

is read out, the SIO simultaneously goes to a receive enable state without having to write dummy data

to the transmit buffer register back again.

(e) Serial data logic switch function (UART2)

When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or

reading from receive buffer register, data is reversed. Figure 1.15.16 shows the example of serial data

logic switch timing.

Figure 1.15.16. Serial data logic switch timing

Transfer clock

TxD2

(no reverse)

TxD2

(reverse)

ÄWhen LSB first

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