HT80C51 User Manual
80C51 Family Instruction Set – 80C51 Instruction Set Summary
Handshake Solutions
© Philips Electronics N.V. 2005
Page 87 of 132
6.
80C51 Family Instruction Set
6.1.
80C51 Instruction Set Summary
Instructions that affect flag settings(1)
Instruction
Flag
Instruction
Flag
C
OV
AC
C
OV
AC
ADD
X
X
X
CLR
C
0
ADDC
X
X
X
CPL
C
X
SUBB
X
X
X
ANL
C,bit
X
MUL
0
X
ANL
C,/bit
X
DIV
0
X
ORL
C,bit
X
DA
X
ORL
C,/bit
X
RRC
X
MOV
C,bit
X
RLC
X
CJNE
X
SETB C
1
(1) Note that operations on SFR byte address 208 or bit addresses 209-215 (i.e., the PSW or bits in the PSW) will also
affect flag settings.
Notes on instruction set and addressing modes:
Rn
Register R7-R0 of the currently selected Register Bank.
direct
8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a
SFR [i.e., I/O port, control register, status register, etc. (128-255)].
@Ri
8-bit internal data RAM location (0-255) addressed indirectly through register R1 or R0.
#data
8-bit constant included in the instruction.
#data 16
16-bit constant included in the instruction
addr 16
16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the
64k-byte Program Memory address space.
addr 11
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2k-byte
page of program memory as the first byte of the following instruction.
Rel
Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is
–128 to +127 bytes relative to first byte of the following instruction.
Bit
Direct Addressed bit in Internal Data RAM or Special Function Register.
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