HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Handshake Solutions
© Philips Electronics N.V. 2005
Page 55 of 132
D7
D6
D5
D4
D3
D2
D1
D0
A
SDA
SCL
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
D7
D6
D5
D4
D3
D2
D1
D0
(3)
A
(1)
(1)
SHIFT ACK&
S1DAT
ACK
S1DAT
SHIFT BSD7
BSD7
LOADED BY THE CPU
SHIFT IN
SHIFT OUT
(1) Valid data in S1DAT
(2) Shifting data in S1DAT and ACK
(3) High level on SDA
[Figure 20] Shift-in and Shift-out Timing
In the following text, it is assumed that ENS1 = “1”.
The “START” Flag, STA
STA = “1”:
When the STA bit is set to enter a Master mode, the SIO1 hardware checks the status
of the I2C bus and generates a START condition if the bus is free. If the bus is not
free, then SIO1 waits for a STOP condition (which will free the bus) and generates a
START condition after a delay of half a clock period of the internal serial clock genera-
tor.
If STA is set while SIO1 is already in a Master mode and one or more bytes are trans-
mitted or received, SIO1 transmits a repeated START condition. STA may be set at
any time. STA may also be set when SIO1 is an addressed slave.
STA = “0”:
When the STA bit is reset, no START condition or repeated START condition will be
generated.
The STOP Flag, STO
STO = “1”:
When the STO bit is set while SIO1 is in a Master mode, a STOP condition is transmit-
ted to the I2C bus. When the STOP condition is detected on the bus, the SIO1 hard-
ware clears the STO flag. In a Slave mode, the STO flag may be set to recover from an
error condition. In this case, no STOP condition is transmitted to the I2C bus. How-
ever, the SIO1 hardware behaves as if a STOP condition has been received and
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