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Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Standard Serial Interface (SIO0)
Page 36 of 132
© Philips Electronics N.V. 2005
Timer 1
sio mode
baud rate
clock input
clock frequency
SMOD
C/T1
mode
reload value
0
2M
sio_clk_i
2 MHz
X
X
X
X
2
625k
t01_clk_i
20 MHz
1
X
X
X
1, 3
691.2k
t01_clk_i
11.059 MHz
1
0
2
FFH
1, 3
345.6k
t01_clk_i
11.059 MHz
1
0
2
FEH
1, 3
230.4k
t01_clk_i
11.059 MHz
1
0
2
FDH
1, 3
115.2k
t01_clk_i
11.059 MHz
1
0
2
FAH
1, 3
115.2k
t01_clk_i
1.8432 MHz
1
0
2
FFH
1, 3
19.2k
t01_clk_i
0.9216 MHz
1
0
2
FDH
1, 3
19.2k
t01_clk_i
1.8432 MHz
1
0
2
FAH
1, 3
9.6k
t01_clk_i
1.8432 MHz
0
0
2
FAH
1, 3
4.8k
t01_clk_i
1.8432 MHz
0
0
2
F4H
1, 3
2.4k
t01_clk_i
1.8432 MHz
0
0
2
E8H
1, 3
1.2k
t01_clk_i
1.8432 MHz
0
0
2
D0H
1, 3
137.5
t01_clk_i
1 MHz
0
0
2
1DH
1, 3
110
t01_clk_i
0.5 MHz
0
0
2
72H
1, 3
110
t01_clk_i
1.8432 MHz
0
0
1
FDF4H
[Table 7]
Timer 1 Generated Commonly Used Baud Rates
5.3.4.4.
More About Mode 0
Serial data enters at input pin sio_rxd_i and exits through output pin sio_txd_o. Pin sio_clk_o
outputs the shift clock during transmission. 8 bits are transmitted/received (LSB first). The baud rate is
fixed at the clock input sio_clk_i.[Figure 12] shows a simplified functional diagram of the serial port
in Mode 0. This mode should be used in half duplex operation only.
Transmission is initiated by any instruction that uses SBUF as a destination register. SEND enables the
output of the shift register to be routed to output pin sio_txd_o and also enables shift clock to the
output pin sio_clk_o. The output data is always stable on the rising edge of the shift clock. Every
clock cycle in which SEND is active, the contents of the transmit shift are shifted to the right one posi-
tion.
Reception is initiated by the condition REN = 1 and RI = 0. RECEIVE enables the shift clock to the out-
put pin sio_clk_o. The input data on pin sio_rxd_i is sampled on the falling edge of the shift
clock. Every clock cycle in which RECEIVE is active, the contents of the receive shift register are
shifted to the left one position. At the 8th shift clock cycle RI is set (and RECEIVE is cleared)
Clearing bit REN during reception immediately stops the receiver.
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