HT80C51 datasheet(52/132 Pages) ETC2

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Handshake Solutions

HT80C51 User Manual

Peripheral Modules – I2C Interface (SIO1)

Page 52 of 132

SDA

SCL

SPACE DURATION

(2)

MARK

DURATION

(1)

(3)

(1)

(1) Another service pulls the SCL line low before the SIO1 "mark" duration is complete. The serial clock

generator is immediately reset and commences with the"space" duration by pulling SCL low.

(2) Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into

the wait state until the SCL line is released.

(3) The SCL line is released, and the serial clock generator commences with the mark duration.

[Figure 18] Serial Clock Synchronization

Serial Clock Generator

This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the Master

Transmitter or Master Receiver mode. It is switched off when SIO1 is in a Slave mode. The program-

mable output clock frequencies are: fi2c_clk_i/60 to fi2c_clk_i/256 and the Timer 1 overflow rate divided by

eight. The output clock pulses have a 50% duty cycle unless the clock generator is synchronized with

other SCL clock sources as described above.

Timing and Control

The timing and control logic generates the timing and control signals for serial byte handling. This logic

block provides the shift pulses for S1DAT, enables the comparator, generates and detects start and

stop conditions, receives and transmits acknowledge bits, controls the master and Slave modes, con-

tains interrupt request logic, and monitors the I2C bus status.

Control Register, S1CON

This 7-bit special function register is used by the microcontroller to control the following SIO1 func-

tions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,

and acknowledgment.

Status Decoder and Status Register

The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This

code is unique for each I2C bus status. The 5-bit code may be used to generate vector addresses for

fast processing of the various service routines. Each service routine processes a particular bus status.

There are 26 possible bus states if all four modes of SIO1 are used. The 5-bit status code is latched

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