HT80C51 datasheet(49/132 Pages) ETC2

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HT80C51 User Manual

Peripheral Modules – I2C Interface (SIO1)

Handshake Solutions

Page 49 of 132

The output stages should consist of open drain transistors that can sink 3mA at VOUT < 0.4 V. These

open drain outputs should not have clamping diodes to VDD. Thus, if the device is connected to the

I2C bus and VDD is switched off, the I2C bus is not affected.

Address Register, S1ADR

This 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits)

to which SIO1 will respond when programmed as a slave transmitter or receiver. The LSB (GC) is

used to enable general call address (00H) recognition.

Comparator

The comparator compares the received 7-bit slave address with its own slave address (7 most signifi-

cant bits in S1ADR). It also compares the first received 8-bit byte with the general call address (00H). If

equality is found, the appropriate status bits are set and an interrupt is requested.

Shift Register, S1DAT

This 8-bit special function register contains a byte of serial data to be transmitted or a byte, which has

just been received. Data in S1DAT is always shifted from right to left; the first bit to be transmitted is the

MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of

S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT al-

ways contains the last byte present on the bus.

Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made

with the correct data in S1DAT.

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