Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Serial Peripheral Interface (SPI)
Page 78 of 132
© Philips Electronics N.V. 2005
Master Out Slave In (MOSI)
The MOSI line is configured as an output in a master device (spi_mosi_o) and as an input in a slave
device (spi_mosi_i). It is used to transfer data from the master to a slave, with the most significant
bit sent first.
Serial Clock (SCK)
The serial clock is used to synchronize data movement both in and out of the device through its MOSI
and MISO lines. The master and slave devices are capable of exchanging a byte of information during
a sequence of eight clock cycles. Since the master device generates SCK, this line becomes an input
on a slave device (spi_sck_i) and an output at the master device (spi_sck_o).
As shown in [Figure 29], four possible timing relationships may be chosen by using control bits CPOL
and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the MOSI line a half-cycle before the
clock edge (SCK), in order for the slave device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device,
SPR0 and SPR1 have no effect on the operation of the SPI.
Slave Select (SS)
The slave select input line (spi_ss_n_i) is used to select a slave device. It has to be low prior to
data transactions and must stay low for the duration of the transaction.
The spi_ss_n_i line on the master must be tied high.
1
2
3
4
5
6
7
8
MSB
6
5
4
3
2
1
LSB
1
2
3
4
5
6
MSB
LSB
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
SAMPLE INPUT
(CPHA = 1) DATA OUT
SS (TO SLAVE)
[Figure 29]
Data Clock Timing Diagram
When CPHA = 0, the shift clock is the OR of spi_ss_n_i with SCK. In this clock phase mode,
spi_ss_n_i must go high between successive characters in an SPI message. When CPHA = 1,
spi_ss_n_i may be left low for several SPI characters. In cases where there is only one SPI slave,
its spi_ss_n_i line could be tied to 0 as long as CPHA = 1 clock modes are used.
5.6.4.2.
Standard Interconnections
Due to data direction register control of SPI outputs and the port D wire-OR mode (DWOM) option, the
SPI system can be configured in a variety of ways. Systems with a single bidirectional data path rather
than separate MISO and MOSI paths can be accommodated.
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