Handshake Solutions
HT80C51 User Manual
Memory Organization – Special Function Registers
Page 16 of 132
© Philips Electronics N.V. 2005
PCON
Power Control Register
addr = 87H
reset value =
0XX00000
Bits
7
6
5
4
3
2
1
0
SMOD
-
-
(DPS)
GF1
GF0
PD
IDL
Bit
symbol
Function
PCON.7
SMOD
1:
0:
Double baud rate (see chapter 5.3 “Standard Serial Interface”)
If timer 1 is used to generate the baudrate and the serial interface is
used in modes 1, 2 or 3, then the baudrate is doubled.
The baudrate is not influenced
PCON.6
PCON.5
-
Reserved (write 0, reads 0)
PCON.4
(DPS)
1:
0:
Data pointer select; implemented with dual data pointer option, only,
otherwise reserved bit (write 0, reads 0)
Select DPTR1 for all DPTR accesses (and for DPL and DPH)
select DPTR0 for all DPTR accesses (and for DPL and DPH)
PCON.3
GF1
General-purpose flag bit.
PCON.2
GF0
General-purpose flag bit.
PCON.1
PD
Power-Down bit. Setting this bit activates power-down operation, which
is also indicated at output pin cpu_powerdown_o.
PCON.0
IDL
Idle mode bit. Setting this bit activates idle mode operation, which is
also indicated at output pin cpu_idle_o.
Note: If 1s are written to PD and IDL at the same time, PD takes precedence.
User software should never write 1s to unimplemented bits, since they may be used in other 80C51
Family products.
2.5.6.1.
Idle Mode
An instruction that sets PCON.0 immediately switches into the idle mode, so no further instruction is
executed. The clock signal is gated off from the CPU but not to the Timer and Serial Port functions.
The CPU status is preserved in its entirety; the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain their data during Idle.
The port pins hold the logical states they had at the time Idle was activated.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be
cleared by hardware, terminating the idle mode. The interrupt will be serviced, and following RETI, the
next instruction to be executed will be the one following the instruction that put the device into Idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal op-
eration or during an Idle. For example, an instruction that activates Idle can also set one or both flag
bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the idle mode is with a hardware reset, which starts the processor in the
same manner as a power-on reset.
2.5.6.2.
Power-Down Mode
An instruction that sets PCON.1 immediately switches into the Power Down mode. In the Power Down
mode, the CPU clock and all peripheral clocks can be stopped completely to lower the power con-
sumption. This has to be done be external circuits, which observe the output pin cpu_powerdown_o,
that indicates the power down mode. With the clocks frozen, all functions are stopped, the contents of
the on-chip RAM and Special Function Registers are maintained. The port pins output the values held
by their respective SFRs.
The only exit from Power Down is a hardware reset. Reset redefines all the SFRs, but does not
change the on-chip RAM.
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