Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 54 of 132
© Philips Electronics N.V. 2005
on the SCL line. When a byte has been shifted into S1DAT, the serial data is available in S1DAT, and
the acknowledge bit is returned by the control logic during the ninth clock pulse. Serial data is shifted
out from S1DAT via a buffer (BSD7) on the falling edges of clock pulses on the SCL line.
When the CPU writes to S1DAT, BSD7 is loaded with the content of S1DAT.7, which is the first bit to be
transmitted to the SDA line (see [Figure 20]). After nine serial clock pulses, the eight bits in S1DAT will
have been transmitted to the SDA line, and the acknowledge bit will be present in ACK. Note that the
eight transmitted bits are shifted back into S1DAT.
The Control Register, S1CON
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the
SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a
STOP condition is present on the I2C bus. The STO bit is also cleared when ENS1 = “0”.
7
6
5
4
3
2
1
0
S1CON (D8H)
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
ENS1, the SIO1 Enable Bit:
ENS1 = “0”:
When ENS1 is “0”, the SDA and SCL outputs are in a high impedance state. SDA and
SCL input signals are ignored, SIO1 is in the “not addressed” slave state, and the STO
bit in S1CON is forced to “0”. No other bits are affected.
ENS1 = “1”:
When ENS1 is “1”, SIO1 is enabled.
ENS1 should not be used to temporarily release SIO1 from the I2C bus since, when ENS1 is reset, the
I2C bus status is lost. The AA flag should be used instead (see description of the AA flag in the follow-
ing text).
INTERNAL BUS
8
S1DAT
ACK
BSD7
SDA
SCL
SHIFT PULSES
[Figure 19] Serial Input/Output Configuration
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
