HT80C51 User Manual
Peripheral Modules – Serial Peripheral Interface (SPI)
Handshake Solutions
© Philips Electronics N.V. 2005
Page 77 of 132
DIVIDER
BY 1, 2, 8, 16
SELECT
SPI CONTROL
SPI STATUS REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
SPI CONTROL REGISTER
SPI
interrupt
request
MSTR
SPE
spi_mstr_o
spi_spe_o
internal data
bus
SPI clock (master)
spi_clk_i
spi_ss_n_i
clock
spi_sck_o
spi_sck_i
spi_mosi_i
spi_mosi_o
spi_miso_i
spi_miso_o
MISO
MOSI
SCK
SS
[Figure 28] SPI block diagram
In the master mode, the SCK clock is driven to the output pin spi_sck_o. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift register, at which point eight
clocks are generated to shift the eight bits of data and then SCK goes idle again. Data is shifted out
thru output pin spi_mosi_o and shifted in from input pin spi_miso_i.
In a slave mode, the slave start logic receives a logic low at pin spi_ss_n_i and the clock at input
pin spi_sck_i. Thus, the slave is synchronized with the master. Data from the master is received
serially at the slave MOSI line (spi_mosi_i) and loads the 8-bit shift register. After the 8-bit shift
register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data is written
into the shift register, then the slave waits for a clock train from the master to shift the data out on the
slave’s MISO line (spi_miso_o).
5.6.4.1.
Bitlevel protocol
Master In Slave Out (MISO)
The MISO line is configured as an input in a master device (spi_miso_i) and as an output in a slave
device (spi_miso_o). It is used to transfer data from the slave to the master, with the most significant
bit sent first. The MISO line of a slave device should be placed in the high-impedance state if the slave
is not selected.
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