HT80C51 User Manual
Clocks – CPU Cock
Handshake Solutions
© Philips Electronics N.V. 2005
Page 19 of 132
4.
Clocks
4.1.
CPU Cock
4.1.1.
Clockless (Aynchronous) Cnfiguration
A handshake circuit does not require a clock to work, it simply adapts its speed to the environment
(other blocks, supply voltage, temperature, etc.). This is a complete asynchronous mode of operation
and our standard configuration of the core.
4.1.2.
Clock synchronization (Option HT80C51_CPU_SYNC)
Some applications or programs require a precisely defined timing behavior of the instruction execu-
tion, for instance, when timing or waiting loops are used. For this case an optional synchronization
feature is offered.
With this feature come two additional input pins: cpu_clk_i and cpu_sync_i.
cpu_clk_i delivers the machine clock and thus the speed of the CPU, input cpu_sync_i decides,
whether the CPU should be synchronized to cpu_clk_i or not:
•
In synchronous mode (cpu_sync_i=1), the CPU synchronizes with cpu_clk_i on a machine
cycle basis after each instruction in such a way that the number of clock cycles for that instruc-
tion is the same as the number of machine cycles for a synchronous implementation. Since
there are no clock dividers attached, one cpu_clk_i cycle equals to one machine cycle.
•
In asynchronous mode of operation (cpu_sync_i=0), the CPU runs at its natural speed, and a
slow cpu_clk_i does not slow it down.
4.2.
Peripheral clocks
In a traditional (synchronous) 80C51 system, all clocks for peripherals are derived from the clock for
the CPU or from the CPU’s machine cycle, which is usually 1/12 or 1/6 of the CPU clock frequency,
depending on the implementation of the CPU. Hence all timing specifications like timer overflow times
or baud rates were specified in relation to the CPU clock.
In a handshake design no single, global clock source is needed, the clock for the CPU can even be
omitted (which is the standard configuration for the HT80C51). Thus for each peripheral that needs a
clock, e.g. timers, serial interfaces or the synchronous SFR bus, a dedicated clock input is provided.
So the optimum clock frequency can be supplied to each peripheral, completely independent from all
other clock frequencies. Also note, that there is no internal clock divider implemented (divide by 12 or
6). Thus, compared to a synchronous design, the same timings (e.g. baud rates) can be achieved with
a lower input clock frequency resulting in lower power consumption.
The timing specifications of the peripherals are related to their specific input clock frequencies.
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