Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Interrupt Controller
Page 20 of 132
© Philips Electronics N.V. 2005
5.
Peripheral Modules
For the HT80C51 a number of standard peripherals like timers and serial interfaces exist. They are
compatible to the standard peripherals in synchronous implementations. The peripherals can be or-
dered along with the CPU and are then part of a combined delivery. The following chapters describe
these peripherals in detail with further options (if available) and their SFRs.
5.1.
Interrupt Controller
This module handles the enabling and priority decoding of interrupt requests as well as entering and
leaving the interrupt routines. The number of interrupt inputs can be configured from 0 up to 15.
5.1.1.
Options
The interrupt controller can be ordered by option HT80C51_INT.
The number of interrupt inputs int_req_i can be selected (ordered) by using option
HT80C51_INT_COUNT.
5.1.2.
Special function registers (IEN0 IEN1 IP0 IP1)
The number of implemented SFRs for the interrupt controller and even the number of bits within these
SFRs depends on the selected number of interrupt inputs. For each interrupt input int_req_i[x]
one interrupt enable bit and one interrupt priority bit exists. All interrupt enable bits are collected in two
SFRs: IEN0 and IEN1. All interrupt priority bits are collected in further two SFRs: IP0 and IP1.
If the number of interrupt inputs is greater than 0, SFRs IEN0 and IP0 exist.
If the number of interrupt inputs is greater than 7, SFRs IEN1 and IP1 exist, too.
IEN0
(IE)
Interrupt enable register 0
addr = A8H
reset value = 00H
bits
7
6
5
4
3
2
1
0
EA
IEN0.6
ES1
ES0
ET1
EX1
ET0
EX0
bit
symbol
Function
IEN0.7
EA
1:
0:
General enable/disable control. If EA = 0,
Any individually enabled interrupt will be accepted.
No interrupt is enabled.
IEN0.6
Enable interrupt input int_req_i[6].
IEN0.5
ES1
Enable I2C interrupt (if available) or interrupt input int_req_i[5].
IEN0.4
ES0
Enable UART interrupt (if available) or interrupt input int_req_i[4].
IEN0.3
ET1
Enable timer 1 overflow interrupt (if available) or interrupt input
int_req_i[3].
IEN0.2
EX1
Enable external interrupt from timer 1 (IE1) (if available) or interrupt
input int_req_i[2].
IEN0.1
ET0
Enable timer 0 overflow interrupt (if available) or interrupt input
int_req_i[1].
IEN0.0
EX0
Enable external interrupt from timer 0 (IE0) (if available) or interrupt
input int_req_i[0].
Bit values: 0 = interrupt disabled; 1 = interrupt enabled.
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