HT80C51 datasheet(25/132 Pages) ETC2

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HT80C51 User Manual

Peripheral Modules – Interrupt Controller

Handshake Solutions

Page 25 of 132

A longer response time would result if the request were blocked by one of the 2 previously listed con-

ditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time

obviously depends on the nature of the other interrupt’s service routine. If the instruction in progress is

not in its final cycle, the additional wait time cannot be more the 3 cycles, since the longest instructions

(MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or

IP, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete

the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or

DIV).

Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9

cycles.

5.1.4.

Setting up the Interrupt Controller

To use any of the interrupts in the 80C51 Family, the following three steps must be taken.

Set the EA (enable all) bit in the IE register to 1.

Set the corresponding individual interrupt enable bit in the IE register to 1.

Begin the interrupt service routine at the corresponding Vector Address of that interrupt (see

[Table 2]).

In addition, for external interrupts (input pins t01_int0_n_i and t01_int1_n_i) depending on

whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need

to be set to 1.

ITx = 0 level activated

ITx = 1 transition activated

5.1.4.1.

Assigning a Higher Priority to One or More Interrupts

In order to assign higher priority to an interrupt, the corresponding bit in the IPx register must be set to

Remember that while an interrupt service is in progress, it cannot be interrupted by a lower or same

level interrupt.

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