HT80C51 User Manual
Introduction to HT80C51 – Compatibility
Handshake Solutions
© Philips Electronics N.V. 2005
Page 5 of 132
1.
Introduction to HT80C51
The Handshake Technology 80C51 (referred to as HT80C51) is an improved version of the ultra low-
power 80C51 (known as ulp80C51). This ulp80C51 has been used in several products such as
pagers, game controllers, telephony controllers, and Mifare ProX and SmartMX smart card controllers.
Millions of these ICs have been shipped.
The HT80C51 implementation offers several unique features, which are detailed below.
•
The HT80C51 is extremely low power (the CPU consumes only 0.1 nano joules per instruction).
•
The HT80C51 has very low electromagnetic emission (EME).
•
The HT80C51 has low supply-current peaks (at least a factor five lower than traditional, clocked
implementations), thus facilitating integration with analog and RF circuitry.
•
The HT80C51 CPU consumes zero stand-by power while in sleep mode, yet is immediately
available for full-speed full-functional operation.
•
The HT80C51 has an asynchronous and optionally a synchronous mode of operation. When
both are present, the actual mode can be dynamically selected on an instruction-per-instruction
base. This is controlled via a dedicated input.
•
In asynchronous mode of operation, the CPU runs at its natural speed, and a slow core clock
does not slow it down.
•
In synchronous mode, the CPU synchronizes with a clock on a machine cycle basis after each
instruction in such a way that the number of clock cycles for that instruction is the same as the
number of machine cycles for a synchronous implementation.
•
The HT80C51 core is configurable, and has a range of configuration options, offering selective
instantiations of 80C51 peripherals and customization of memory interfaces.
•
The HT80C51 peripherals consume zero power when not actively used.
•
Optional dual datapointer (for more compact code).
•
Optional MOVC protection (only grants program code from lower program memory permission
to read lower program memory).
1.1.
Compatibility
The HT80C51 implementation is functionally compatible to the instruction set and the peripherals of
the original 80C51.
The HT80C51 and its peripherals have been designed in Haste, which is the high-level programming
language of the Handshake Technology design flow. This design flow is to a large extent technology
independent. Mapping onto various VLSI technologies from different vendors is supported.
For production testing, both functional and scan-test version are supported. The scan-test version is
compatible with standard ATPG tools.
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