HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Handshake Solutions
© Philips Electronics N.V. 2005
Page 59 of 132
Master Receiver mode (not available for slave-only version)
In the Master Receiver mode, a number of data bytes are received from a slave transmitter (see
[Figure 22]). The transfer is initialized as in the Master Transmitter mode. When the start condition has
been transmitted, the interrupt service routine must load S1DAT with the 7-bit slave address and the
data direction bit (SLA+R). The SI bit in S1CON must then be cleared before the serial transfer can con-
tinue.
When the slave address and the data direction bit have been transmitted and an acknowledgment bit
has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are
possible. These are 40H, 48H, or 38H for the Master mode and also 68H, 78H, or B0H if the Slave
mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is
detailed in [Table 11]. ENS1, CR1, and CR0 are not affected by the serial transfer and are not referred to
in Table 5. After a repeated start condition (state 10H), SIO1 may switch to the Master Transmitter
mode by loading S1DAT with SLA+W.
Slave Receiver mode
In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see
[Figure 23]). To initiate the Slave Receiver mode, S1ADR and S1CON must be loaded as follows:
7
6
5
4
3
2
1
0
S1ADR (DBH)
own slave address
GC
The upper 7 bits are the address to which SIO1 will respond when addressed by a master. If the LSB
(GC) is set, SIO1 will respond to the general call address (00H); otherwise it ignores the general call
address.
7
6
5
4
3
2
1
0
S1CON (D8H)
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
X
1
0
0
0
1
X
X
CR0, CR1, and CR2 do not affect SIO1 in the Slave mode. ENS1 must be set to logic 1 to enable SIO1.
The AA bit must be set to enable SIO1 to acknowledge its own slave address or the general call ad-
dress. STA, STO, and SI must be reset.
When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave ad-
dress followed by the data direction bit which must be “0” (W) for SIO1 to operate in the Slave Re-
ceiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (I)
is set and a valid status code can be read from S1STA. This status code is used to vector to an inter-
rupt service routine, and the appropriate action to be taken for each of these status codes is detailed
in [Table 12]. The Slave Receiver mode may also be entered if arbitration is lost while SIO1 is in the
Master mode (see status 68H and 78H).
If the AA bit is reset during a transfer, SIO1 will return a not acknowledge (logic 1) to SDA after the
next received data byte. While AA is reset, SIO1 does not respond to its own slave address or a gen-
eral call address. However, the I2C bus is still monitored and address recognition may be resumed at
any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the
I2C bus.
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