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HT80C51 датащи(PDF) 72 Page - List of Unclassifed Manufacturers

номер детали HT80C51
подробное описание детали  User Manual Document Information
PDF  132 Pages
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HT80C51 датащи(HTML) 72 Page - List of Unclassifed Manufacturers

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Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 72 of 132
© Philips Electronics N.V. 2005
TIME OUT
STA FLAG
SDA LINE
SCL LINE
START CONDITION
[Figure 26] Forced Access to a Busy I2C Bus
I2C Bus Obstructed by a Low Level on SCL or SDA
An I2C bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the SCL line is
obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the SIO1
hardware cannot resolve this type of problem. When this occurs, the problem must be resolved by the
device that is pulling the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit synchroniza-
tion), the problem can be solved by transmitting additional clock pulses on the SCL line (see [Figure
27]). The SIO1 hardware transmits additional clock pulses when the STA flag is set, but no START
condition can be generated because the SDA line is pulled LOW while the I2C bus is considered free.
The SIO1 hardware attempts to generate a START condition after every two additional clock pulses
on the SCL line. When the SDA line is eventually released, a normal START condition is transmitted,
state 08H is entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed
(pulled LOW), the SIO1 hardware performs the same action as described above. In each case, state
08H is entered after a successful START condition is transmitted and normal serial transfer continues.
Note that the CPU is not involved in solving these bus hang-up problems.
Bus Error
A bus error occurs when a START or STOP condition is present at an illegal position in the format
frame. Examples of illegal positions are during the serial transfer of an address byte, a data, or an
acknowledge bit.
The SIO1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master
or an addressed slave. When a bus error is detected, SIO1 immediately switches to the “not ad-
dressed” Slave mode, releases the SDA and SCL lines, sets the interrupt flag, and loads the status
register with 00H. This status code may be used to vector to a service routine which either attempts
the aborted serial transfer again or simply recovers from the error condition as shown in [Table 14].



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