Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Watchdog Timer (under development)
Page 80 of 132
© Philips Electronics N.V. 2005
5.7.
Watchdog Timer (under development)
This module comprises an 8bit watchdog timer with prescaler.
5.7.1.
Options
The watchdog timer can be selected (ordered) by using option t.b.d. .
5.7.2.
Special function registers (T3)
T3
watchdog timer register
addr =
reset value =
bits
7
6
5
4
3
2
1
0
T3
bit
Symbol
Function
T3.7 ..
T3.0
Watchdog timer count register. Specifies the interval until the next timer
overflow. Writeable, when input wdt_ena_i = 1.
5.7.3.
Interrupts
No interrupts are generated.
If the watchdog timer expires, a pulse on the reset output wdt_rst_o is generated.
5.7.4.
Operation
The Watchdog Timer consists of an 11-bit prescaler and an 8-bit timer.
It is controlled by the Watchdog Enable pin (wdt_ena_i). When wdt_ena_i = 1, the timer is enabled
and the Power-down mode is disabled. When wdt_ena_i = 0, the timer is disabled and the Power-
down mode is enabled. In the Idle mode the Watchdog Timer and reset circuitry remain active.
The Watchdog Timer is shown in 0.
The timer interval is derived from the frequency of clock input wdt_clk_i using the following formula:
watchdog time interval =
()
i
clk
wdt
f
T
_
_
3
256
2048
−
×
When a timer overflow occurs, a reset output pulse is generated at the pin wdt_rst_o for 3 clock
cycles.
To prevent a system reset the timer must be reloaded in time by the application software. If the proc-
essor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the processor running out of control.
The Watchdog Timer can only be reloaded if the condition flag WLE (PCON.4) has been previously set
by software. At the moment the counter is loaded the condition flag is automatically cleared.
The time interval between the timer reloading and the occurrence of a reset is dependent upon the
reloaded value. For example, this time period may range from 2 ms to 500 ms when using a clock
frequency fwdt_clk_i = 1 MHz.
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