HT80C51 User Manual
Peripheral Modules – Interrupt Controller
Handshake Solutions
© Philips Electronics N.V. 2005
Page 23 of 132
[Table 2]
Interrupt Signals, Vectors and Priorities.
5.1.3.2.
How Interrupts Are Handled
The interrupt flags are sampled at every start of an instruction. The samples are polled at the start of
the following instruction. If one of the flags was in a set condition at the preceding cycle, the polling
cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine,
provided this hardware-generated LCALL is not blocked by any of the following conditions:
1.
An interrupt of equal or higher priority level is already in progress.
2.
The instruction in progress is RETI or any write to the IENx or IPx registers.
Any of these two conditions will block the generation of the LCALL to the interrupt service routine.
Condition 2 ensures that if the instruction in progress is RETI or any access to IENx or IPx, then at least
one more instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with each new instruction, and the values polled are the values that were
present at the start of the previous instruction. Note that if an interrupt flag is active but not being re-
sponded to for one of the above conditions, if the flag is not still active when the blocking condition is
removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was
once active but not serviced is not remembered. Every polling cycle is new.
interrupt
interrupt
input
standard internal
connection
(if peripheral is selected)
vector
address
enable
priority
select
priority
within
level
int 0
int_req_i[0]
IE0
timer 0
0003H
IEN0.0
IP0.0
highest
int 1
int_req_i[1]
TF0
timer 0
000BH
IEN0.1
IP0.1
int 2
int_req_i[2]
IE1
timer 1
0013H
IEN0.2
IP0.2
int 3
int_req_i[3]
TF1
timer 1
001BH
IEN0.3
IP0.3
int 4
int_req_i[4]
RI or TI
SI0(UART)
0023H
IEN0.4
IP0.4
int 5
int_req_i[5]
SI
I2C
002BH
IEN0.5
IP0.5
int 6
int_req_i[6]
SPIF
SPI
0033H
IEN0.6
IP0.6
int 7
int_req_i[7]
003BH
IEN1.0
IP1.0
int 8
int_req_i[8]
0043H
IEN1.1
IP1.1
int 9
int_req_i[9]
004BH
IEN1.2
IP1.2
int 10
int_req_i[10]
0053H
IEN1.3
IP1.3
int 11
int_req_i[11]
005BH
IEN1.4
IP1.4
int 12
int_req_i[12]
0063H
IEN1.5
IP1.5
int 13
int_req_i[13]
006BH
IEN1.6
IP1.6
int 14
int_req_i[14]
0073H
IEN1.7
IP1.7
lowest
Note: The “priority within level” structure is only used to resolve simultaneous requests of the
same priority level.
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
