Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 70 of 132
© Philips Electronics N.V. 2005
application software response
to S1CON
status
code
S1STA
status of the I2C bus
and SIO1 hardware
to/from S1DAT
STA STO
SI
AA
next action taken by SIO1 hardware
F8H
No relevant state informa-
tion available; SI = 0
No S1DAT action
No S1CON action
Wait or proceed current transfer
00H
Bus error during MST or
selected Slave modes, due
to an illegal START or
STOP condition. State 00H
can also occur when
interference causes SIO1
to enter an undefined state.
No S1DAT action
0
1
0
X
Only the internal hardware is affected in the MST
or addressed SLV modes. In all cases, the bus is
released and SIO1 is switched to the not ad-
dressed SLV mode. STO is reset.
[Table 14] Miscellaneous States
5.5.4.5.
Miscellaneous States
There are two S1STA codes that do not correspond to a defined SIO1 hardware state (see [Table 14]).
These are discussed below.
S1STA = F8H
This status code indicates that no relevant information is available because the serial interrupt flag, SI,
is not yet set. This occurs between other states and when SIO1 is not involved in a serial transfer.
S1STA = 00H
This status code indicates that a bus error has occurred during an SIO1 serial transfer. A bus error is
caused when a START or STOP condition occurs at an illegal position in the format frame. Examples
of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowl-
edge bit. A bus error may also be caused when external interference disturbs the internal SIO1 sig-
nals. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI
must be cleared. This causes SIO1 to enter the “not addressed” Slave mode (a defined state) and to
clear the STO flag (no other bits in S1CON are affected). The SDA and SCL lines are released (a STOP
condition is nottransmitted).
5.5.4.6.
Some Special Cases
The SIO1 hardware has facilities to handle the following special cases that may occur during a serial
transfer.
Simultaneous Repeated START Conditions from Two Masters
A repeated START condition may be generated in the Master Transmitter or Master Receiver modes.
A special case occurs if another master simultaneously generates a repeated START condition (see
[Figure 25]). Until this occurs, arbitration is not lost by either master since they were both transmitting
the same data.
If the SIO1 hardware detects a repeated START condition on the I2C bus before generating a re-
peated START condition itself, it will release the bus, and no interrupt request is generated. If another
master frees the bus by generating a STOP condition, SIO1 will transmit a normal START condition
(state 08H), and a retry of the total serial data transfer can commence.
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