Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Interrupt Controller
Page 22 of 132
© Philips Electronics N.V. 2005
IP1
Interrupt priority register 1
addr = F8H
reset value = 00H
bits
7
6
5
4
3
2
1
0
IP1.7
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
bit
symbol
Function
IP1.7
Priority level for interrupt input int_req_i[14].
IP1.6
Priority level for interrupt input int_req_i[13].
IP1.5
Priority level for interrupt input int_req_i[12].
IP1.4
Priority level for interrupt input int_req_i[11].
IP1.3
Priority level for interrupt input int_req_i[10].
IP1.2
Priority level for interrupt input int_req_i[9].
IP1.1
Priority level for interrupt input int_req_i[8].
IP1.0
Priority level for interrupt input int_req_i[7].
Bit values: 0 = low priority; 1 = high priority.
5.1.3.
Operation
The HT80C51 provides up to 15 interrupt inputs. Depending on the configuration of standard periph-
erals, some of these inputs are already internally connected to interrupt sources in these peripherals.
For a description of these interrupt sources, please, see the description of the peripheral blocks.
[Table 2] shows these default connections.
All of the bits that generate interrupts can be set or cleared by software, with the same result as
though it had been set or cleared by hardware. That is, interrupts can be generated or pending inter-
rupts can be canceled in software.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in
Special Function Registers IEN0 and IEN1. IEN0 also contains a global disable bit, EA, which disables all
interrupts at once.
5.1.3.1.
Interrupt Priority Level Structure
Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in Special Function Registers IP0 and IP1. A low-priority interrupt can itself be interrupted
by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be
interrupted by any other interrupt source.
If two requests of different priority levels are received simultaneously, the request of higher priority
level is serviced. If requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus within each priority level there is a second prior-
ity structure determined by the polling sequence, as summarized in [Table 2].
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