Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 44 of 132
© Philips Electronics N.V. 2005
5.5.
I2C Interface (SIO1)
The Handshake Technology I2C (referred to as HT-I2C) is a low power version of the standard 80C51
I2C (as used in the 8XC552 80C51).
The HT-I2C implementation offers several unique features, which are detailed below.
•
The HT-I2C consumes almost zero stand-by power while in sleep mode, yet is immediately
available for full-speed full-functional operation.
•
The HT-I2C has very low electromagnetic emission (EME).
•
The HT-I2C has low supply-current peaks, thus facilitating integration with analog and RF cir-
cuitry.
•
The HT-I2C use a dedicated special function register (HT-SFR) bus for interconnects with the
HT80C51 micro-controller.
5.5.1.
Options
A master-slave combination of the I2C interface can be ordered by option HT80C51_I2C.
A slave-only I2C interface can be ordered by using option HT80C51_I2C_SLAVEONLY.
5.5.2.
Special function registers (S1CON S1ADR S1DAT S1STA )
S1CON
SIO1 control register
addr = D8H
reset value = 00H
bits
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
bit
symbol
Function
S1CON.7
CR2
Clock rate bit 2 (not implemented in slave-only version)
S1CON.6
ENS1
1:
0:
SIO1 enable bit
SIO1 enabled
SIO1 disabled
S1CON.5
STA
STArt flag, starts transmission (not implemented in slave-only version)
S1CON.4
STO
STOp flag, stops transmission
S1CON.3
SI
Serial Interrupt; set by hardware, when an interrupt request is gener-
ated; must be reset be software
S1CON.2
AA
1:
0:
Assert Acknowledge flag; type of acknowledge to be returned
return NOT ACK
return ACK
S1CON.1
CR1
Clock rate bit 1 (not implemented in slave-only version)
S1CON.0
CR0
Clock rate bit 0 (not implemented in slave-only version)
Note: For “not implemented” bits always write 0s, read accesses always return 0.
The master and slave operate on a common clock signal, which depends on the actual values of the
signals CR0, CR1 and CR2. Changing one or more of the following bits CR0, CR1 or CR2 during a data
transfer may lead to unpredictable results. The baud rates are derived from a dedicated clock input pin
(i2c_clk_i).
Note: Baud rate generation and clock input pin (i2c_clk_i) are not available for the slave-only ver-
sion.
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