Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Serial Peripheral Interface (SPI)
Page 74 of 132
© Philips Electronics N.V. 2005
5.6.
Serial Peripheral Interface (SPI)
This serial peripheral interface is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. The main features are:
•
Full Duplex, Three-Wire Synchronous Transfers
•
Master or Slave Operation
•
Four Programmable Master Bit Rates
•
Programmable Clock Polarity and Phase
•
End-of-Transmission Interrupt Flag
•
Write Collision Flag Protection
5.6.1.
Options
The SPI interface can be selected (ordered) by using option HT80C51_SPI .
5.6.2.
Special function registers (SPCR SPSR SPDR)
SPCR
SPI control register
addr = F5H
reset value = 0000
0100
bits
7
6
5
4
3
2
1
0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
bit
Symbol
Function
SPCR.7
SPIE
1:
0:
SPI interrupt enable
SPI interrupt enabled: SFR bit SPIF causes an SPI interrupt
(int_req_i[6])
SPI interrupt disabled: no SPI interrupt generated
SPCR.6
SPE
1:
0:
SPI interface enable
SPI interface enabled, output pin spi_spe_o is 1
SPI interface disabled, output pin spi_spe_o is 0
SPCR.5
DWOM
1:
0:
Port D Wire-OR Mode; connected to output pin spi_dwom_o.
The environment can use the signal of this output pin to select the
output mode:
spi_dwom_o = 1: use open drain outputs
spi_dwom_o = 0: use standard CMOS outputs
DWOM is not used by the SPI interface internally.
SPCR.4
MSTR
1:
0:
Master mode select
master mode
slave mode
SPCR.3
CPOL
1:
0:
Clock Polarity; selects the polarity of the shift clock (spi_sck_o in
master mode, spi_sck_i in slave mode) (see [Figure 29])
shift clock is active low
shift clock is active high
SPCR.2
CPHA
1:
0:
Clock phase
As soon as input pin spi_ss_n_i goes low, the transaction begins and
the first edge of spi_sck_i invokes the first data sample.
If input pin spi_ss_n_i is 0, the outputs are enabled.
SPCR.1
SPCR.0
SPR1
SPR0
Baudrate select bits.
In master mode these bits select the clock divisor for generating the
clock output spi_sck_o (see table below).
In slave mode these bits have no effect.
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